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ADSP-2104 Datasheet(PDF) 1 Page - Analog Devices

Part No. ADSP-2104
Description  Low Cost DSP Microcomputers
Download  36 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADSP-2104 Datasheet(HTML) 1 Page - Analog Devices

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FUNCTIONAL BLOCK DIAGRAM
EXTERNAL
ADDRESS
BUS
DATA
MEMORY
PROGRAM
MEMORY
EXTERNAL
DATA
BUS
ADSP-2100 CORE
ARITHMETIC UNITS
SHIFTER
MAC
ALU
MEMORY
SERIAL PORTS
SPORT 0
SPORT 1
DATA ADDRESS
GENERATORS
DAG 1
DAG 2
PROGRAM
SEQUENCER
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
TIMER
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Low Cost DSP Microcomputers
ADSP-2104/ADSP-2109
SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus & Dual Data Buses
Independent Computation Units: ALU, Multiplier/
Accumulator, and Shifter
Single-Cycle Instruction Execution & Multifunction
Instructions
On-Chip Program Memory RAM or ROM
& Data Memory RAM
Integrated I/O Peripherals: Serial Ports and Timer
FEATURES
20 MIPS, 50 ns Maximum Instruction Rate
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory (e.g., EPROM )
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering, and Multichannel Operation
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PLCC Package
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
GENERAL DESCRIPTION
The ADSP-2104 and ADSP-2109 processors are single-chip
microcomputers optimized for digital signal processing (DSP)
and other high speed numeric processing applications. The
ADSP-2104/ADSP-2109 processors are built upon a common
core. Each processor combines the core DSP architecture—
computation units, data address generators, and program
sequencer—with differentiating features such as on-chip
program and data memory RAM (ADSP-2109 contains 4K
words of program ROM), a programmable timer, and two
serial ports.
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the ADSP-2104/ADSP-2109 operates at
20 MIPS with a 50 ns instruction cycle time. The ADSP-2104L
and ADSP-2109L are 3.3 volt versions which operate at
13.824 MIPS with a 72.3 ns instruction cycle time. Every
instruction can execute in a single cycle. Fabrication in CMOS
results in low power dissipation.
The ADSP-2100 Family’s flexible architecture and compre-
hensive instruction set support a high degree of parallelism.
In one cycle the ADSP-2104/ADSP-2109 can perform all
of the following operations:
Generate the next program address
Fetch the next instruction
Perform one or two data moves
Update one or two data address pointers
Perform a computation
Receive and transmit data via one or two serial ports
The ADSP-2104 contains 512 words of program RAM, 256
words of data RAM, an interval timer, and two serial ports.
The ADSP-2104L is a 3.3 volt power supply version of the
ADSP-2104; it is identical to the ADSP-2104 in all other
characteristics.
The ADSP-2109 contains 4K words of program ROM and
256 words of data RAM, an interval timer, and two serial ports.
The ADSP-2109L is a 3.3 volt power supply version of the
ADSP-2109; it is identical to the ADSP-2109 in all other
characteristics.


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