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ADP3605 Datasheet(PDF) 6 Page - Analog Devices |
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ADP3605 Datasheet(HTML) 6 Page - Analog Devices |
6 / 8 page ADP3605 –6– REV. A Pump Capacitor The ADP3605 alternately charges CP to the input voltage when CP is switched in parallel with the input supply, and then trans- fers charge to CO when CP is switched in parallel with CO. During the time CP is charging, the peak current is approxi- mately two times the output current. During the time CP is delivering charge to CO, the supply cur- rent drops down to about 3 mA. A low ESR capacitor has much greater impact on performance for CP than CO since current through CP is twice the CO cur- rent. Therefore, the voltage drop due to CP is about four times the ESR of CP times the load current. While the ESR of CO affects the output ripple voltage, the voltage drop generated by the ESR of CP, combined with the voltage drop due to the output source resistance, determines the maximum available VOUT. TEMPERATURE – C 10 1.0 0.01 –50 100 0 50 0.1 ALUMINUM CERAMIC TANTALUM ORGANIC SEMIC Figure 13. ESR vs. Temperature CAPACITANCE – F 100 80 0 0 160 20 40 60 80 100 120 140 60 40 20 ADP3605-3 150m 100m 50m Figure 14. Output Ripple Voltage (mV) vs. Capacitance and ESR Improved Load Regulation In most applications, the IR drop from printed circuit board traces is not critical. VSENSE should be connected to the output at a convenient PCB location close to the load. However, if a reduction in IR drop or improvement in load regulation is de- sired, the sense line can be used to monitor the output voltage at the load. To avoid excessive noise pickup, keep the VSENSE line as short as possible and away from any noisy line. Shutdown Mode The ADP3605’s output can be disabled by pulling the SD pin (Pin 4) high to a TTL/CMOS logic compatible level which will stop the internal oscillator. In shutdown mode, the quiescent current is reduced to 2 µA (typical). Applying a digital low level or tying the SD Pin to ground will turn on the output. If the shutdown feature is not used, Pin 4 should be tied to the ground pin. Power Dissipation The power dissipation of the ADP3605 circuit must be limited such that the junction temperature of the device does not exceed the maximum junction temperature rating. Total power dissipa- tion is calculated as follows: P = (VIN –|VOUT|) IOUT + (VIN) IS Where IOUT and IS are output current and supply current, VIN and VOUT are input and output voltages respectively. For example: assuming worst case conditions, VIN = 6 V, VOUT = –2.9 V, IOUT = 120 mA and IS = 5 mA. Calculated device power dissipation is: P ≈ (6 V–|–2.9 V|)(0.12) + (6 V)(0.005 A) = 402 mW This is far below the 660 mW power dissipation capability of the ADP3605 in SO-8 or 600 mW in RU-14 General Board Layout Guidelines Since the ADP3605’s internal switches turn on and off very fast, good PC board layout practices are critical to ensure optimal operation of the device. Improper layouts will result in poor load regulation, especially under heavy loads. Following these simple layout guidelines will improve output performance. 1. Use adequate ground and power traces or planes. 2. Use single point ground for device ground and input and output capacitor grounds. 3. Keep external components as close to the device as possible. 4. Use short traces from the input and output capacitors to the input and output pins respectively. |
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