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ADP3422 Datasheet(PDF) 2 Page - Analog Devices

Part No. ADP3422
Description  IMVP-II-Compliant Core Power Controller for Mobile CPUs
Download  16 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
Logo AD - Analog Devices

ADP3422 Datasheet(HTML) 2 Page - Analog Devices

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REV. 0
–2–
ADP3422–SPECIFICATIONS
(0
≤ TA ≤ 85 C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, VCOREFB = VDAC
(
VDACOUT), VREG = VCS– = VVID = 1.25 V, VCPUSET = 0 V, ROUT = 100 k , COUT = 10 pF, CSS = 47 nF, RPWRGD = 5 k
to VCC, RCLAMP = 5.1 k
to VCC, HYSSET, BSHIFT, DSHIFT, and FSHIFT are open,
BOM = H, DSLP = H, DPRSLP = L, SWFB = L, unless otherwise noted. Current sunk
by a pin has a positive sign, sourced by a pin has a negative sign.)
ELECTRICAL CHARACTERISTICS
1
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY-UVLO-SHUTDOWN
Normal Supply Current
ICC
615
mA
UVLO Supply Current
ICC(UVLO)
200
µA
Shutdown Supply Current
ICCSD
SD = L
1
µA
UVLO Threshold
VCCH
VCC Rising Up, VSS = 0 V
2.95
V
VCCL
VCC Falling, VSS Floating
2.7
V
UVLO Hysteresis
VCCHYS
50
mV
Shutdown Threshold (CMOS Input)
VSDTH
VCC/2
POWERGOOD
Core Feedback Threshold Voltage
VCOREFBH
0.9 V < VDAC < 1.675 V
VCOREFB Rising
1.12 VDAC
1.145 VDAC
V
VCOREFB Falling
1.095 VDAC
1.12 VDAC
V
VCOREFB Rising
0.88 VDAC
0.905 VDAC
V
VCOREFB Falling
0.855 VDAC
0.88 VDAC
V
PowerGood Output Voltage
VPWRGD
VCOREFB = VDACOUT
0.95 VCC
VCC
V
(Open Drain Output)
VCOREFB = 0.8 VDACOUT
0
0.8
V
Blanking Time
tPWRGD,BLNK
2
VCC = 3.3 V
100
µs
SOFT-START/HICCUP TIMER
Charge/Discharge Current
ISS
VSS = 0.5 V
–16
µA
VSS = 0.5 V, VCC = 2.5 V
0.6
µA
Soft-Start Enable/Hiccup
VSSEN
VREG = 1.25 V,
Termination Threshold
VRAMP = VCOREFB = 1.27 V
VSS Falling
150
200
mV
VSS Rising
200
mV
Soft-Start Termination/Hiccup
VSSTERM
VRAMP = VCOREFB = 1.27 V
Enable Threshold
VSS Rising
2.05
V
VSS Falling
2.0
V
VID DAC
VID Input Threshold (CMOS Inputs) VVID0...4
0.8
0.7 VCC
V
VID Input Current
IVID0...4
VID 0...4 = L
10
40
µA
(Internal Active Pull-up)
Output Voltage
VDAC
See VID Code Table 1
0.600
1.750
V
Output Voltage Accuracy
VDAC/VDAC
–0.85
+0.85
%
Output Voltage Settling Time
3
tDACS
4
1.3
µs
CORE COMPARATOR
Input Offset Voltage
VCOREOS
VREG = 1.25 V
±1.5
mV
Input Bias Current
IREG
VREG = VRAMP = 1.25 V
±0.3
µA
Output Voltage
VOUT_H
VCC = 3.0 V
2.5
3.0
V
VOUT_L
VCC = 3.6 V
0
0.4
V
Propagation Delay Time
3
tRMPOUT_PD
5
50
ns
Rise and Fall Time2
tOUT_R
6
310
ns
tOUT_F
6
310
ns
Blanking Time
tBLNK
OUT L-H Transition
75
ns
OUT H-L Transition
140
ns
Switch Feedback Threshold
VSWFB_TH
VCC/2
V
(CMOS Input)


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