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ADP3203 Datasheet(PDF) 2 Page - Analog Devices

Part No. ADP3203
Description  2-Phase IMVP-II & IMVP-III Core Controller for Mobile CPUs
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADP3203 Datasheet(HTML) 2 Page - Analog Devices

 
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REV. PrD
–2–
PRELIMINARY TECHNICAL DATA
ADP3203–SPECIFICATIONS
1
Parameter
Symbol
Conditions
Min
Typ
Max
Units
SUPPLY-UVLO-SHUTDOWN
Normal Supply Current
I
CC
715
mA
UVLO Supply Current
I
CCUVLO
425
µA
Shutdown Supply Current
I
CCSD
SD = L, 3.0 V
≤≤≤≤≤ VCC ≤≤≤≤≤ 3.6 V
10
µA
UVLO Threshold
SD = H
V
CCH
V
CC ramping up, VSS= 0 V
2.9
V
V
CCL
V
CC ramping down,
2.65
V
V
SS floating
UVLO Hysteresis
V
CCHYS
50
mV
Shutdown Threshold (CMOS Input)
V
SDTH
V
CC/2
V
POWERGOOD-CORE FEEDBACK
Core Feedback Threshold Voltage
V
COREFBH
0.9 V < V
DAC < 1.675 V
V
COREFB ramping up
1.12 V
DAC
1.14 V
DAC
V
V
COREFB ramping down
1.10 V
DAC
1.12 V
DAC
V
V
COREFB ramping up
0.88 V
DAC
0.90 V
DAC
V
V
COREFB ramping down
0.86 V
DAC
0.88 V
DAC
V
Power Good Output Voltage
V
PWRGD
V
COREFB = VDACOUT
0.95 V
CC
V
CC
V
(open drain output)
V
COREFB = 0.8 VDACOUT
0
0.8
V
Masking Time
2
t
PWRGD,MSK
6
V
CC = 3.3 V
100
µs
SOFT-START/HICCUP TIMER
Charge/Discharge Current
I
SS
V
SS = 0 V
16
µA
V
SS = 0.5 V
0.5
µA
Soft-Start Enable/Hiccup
V
REG = 1.25 V,
Termination Threshold
V
RAMP = VCOREFB = 1.27 V
V
SSENDWN
V
SS ramping down
80
200
mV
V
SSENUP
7
V
SS ramping up
150
mV
Soft-Start Termination/Hiccup
V
SSTERM
V
RAMP = VCOREFB = 1.27 V
Enable Threshold
V
SS ramping up
1.75
2.00
2.25
V
VID DAC
VID Input Threshold (CMOS Inputs)
V
VID0..4
V
CC/2
V
VID Input Current
I
VID0..4
VID 0..4 = L
90
µA
(Internal Active Pull-up)
Output Voltage
V
DAC
See VID Code Table 1
0.600
1.750
V
Accuracy
∆V
DAC/VDAC
0.850 V < V
DAC < 1.750 V
–1.0
+1.0
%
0.600 V < V
DAC < 0.825 V
–8.5
+8.5
mV
Settling Time
2
t
DACS
3
∆V
DAC = 0.5 V, CDAC = 10 nF
3.5
µs
Notes:
1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2 Guaranteed by characterization.
3 Measured from 50% of VID code transition amplitude to the point where V
DACOUT settles within ±1% of its steady state value.
4 40 mV
PP amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to
50% of the output voltage swing.
5 Measured between the 30% and 70% points of the output voltage swing.
6 Two test conditions: 1)PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (V
COREFB,BAD = 1.0 V at VVID = 1.25 V setting) to
the COREFB pin right after the moment that
BOM or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking
delay time. 2) PWRGD is forced to fail (V
COREFB,BAD = 1.0 V at VVID = 1.25 V setting) but gets into the CoreGood-window
(V
COREFB,GOOD = 1.25 V) right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified
blanking delay time.
7Guaranteed by design.
( T
A
===== 25 °C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, V
COREFB =
V
DAC (
≡ V
DACOUT), VREG = VCS– = VVID = 1.25 V, ROUT = 100 k
Ω, C
OUT = 10 pF,
C
SS = 47 nF, RPWRGD = 680
Ω to 1.2 V, R
CLAMP = 5.1 k
Ω to VCC, HYSSET, BSHIFT,
DSHIFT are open, BOM = H, DSLP = H, DPRSLP = L, unless otherwise noted) Current sunk by a pin has a positive sign, sourced by a pin has a
negative sign. Negative sign is disregarded for min and max values.


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