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ADP1073 Datasheet(PDF) 5 Page - Analog Devices

Part No. ADP1073
Description  Micropower DC.DC Converter Adjustable and Fixed 3.3 V, 5 V, 12 V
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADP1073 Datasheet(HTML) 5 Page - Analog Devices

 
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ADP1073
–5–
REV. 0
TEMPERATURE – C
2300
2100
1100
40
085
25
70
1900
1700
1500
1300
VIN = 1.5V
RL = 100k
Figure 11. “Gain Block” Gain vs. Temperature
THEORY OF OPERATION
The ADP1073 is a flexible, low power switch mode power
supply (SMPS) controller. The regulated output voltage can be
greater than the input voltage (boost or step-up mode) or less
than the input (buck or step-down mode). This device uses a
gated-oscillator technique to provide very high performance
with low quiescent current.
A functional block diagram of the ADP1073 is shown on the
front page. The internal 212 mV reference is connected to one
input of the comparator, while the other input is externally
connected (via the FB pin) to a feedback network connected to
the regulated output. When the voltage at the FB pin falls below
212 mV, the 19 kHz oscillator turns on. A driver amplifier pro-
vides base drive to the internal power switch and the switching
action raises the output voltage. When the voltage at the FB pin
exceeds 212 mV, the oscillator is shut off. While the oscillator is
off, the ADP1073 quiescent current is only 100
µA. The com-
parator includes a small amount of hysteresis, which ensures
loop stability without requiring external components for fre-
quency compensation.
The maximum current in the internal power switch can be set
by connecting a resistor between VIN and the ILIM pin. When
the maximum current is exceeded, the switch is turned OFF.
The current limit circuitry has a time delay of about 2
µs. If an
external resistor is not used, connect ILIM to VIN. Further infor-
mation on ILIM is included in the Limiting the Switch Current
section of this data sheet.
The ADP1073 internal oscillator provides 38
µs ON and 15 µs
OFF times, which is ideal for applications where the ratio be-
tween VIN and VOUT is roughly a factor of three (such as gener-
ating +5 V from a single 1.5 V cell). Wider range conversions,
as well as step-down converters, can also be accomplished with
a slight loss in the maximum output power that can be obtained.
An uncommitted gain block on the ADP1073 can be connected
as a low-battery detector, linear post-regulator or undervoltage
lockout detector. The inverting input of the gain block is inter-
nally connected to the 212 mV reference. The noninverting
input is available at the SET pin. A resistor divider, connected
between VIN and GND with the junction connected to the SET
pin, causes the AO output to go LOW when the input voltage
goes below the low battery set point. The AO output is an open
collector NPN transistor that can sink 100
µA.
The ADP1073 provides external connections for both the col-
lector and emitter of its internal power switch, which permits
both step-up and step-down modes of operation. For the step-
up mode, the emitter (Pin SW2) is connected to GND and the
collector (Pin SW1) drives the inductor. For step-down mode,
the emitter drives the inductor while the collector is connected
to VIN.
The output voltage of the ADP1073 is set with two external
resistors. Three fixed-voltage models are also available:
ADP1073-3.3 (+3.3 V), ADP1073-5 (+5 V) and ADP1073-12
(+12 V). The fixed-voltage models are identical to the ADP1073,
except that laser-trimmed voltage-setting resistors are included
on the chip. Only three external components are required to
form a +3.3 V, +5 V or +12 V converter. On the fixed-voltage
models of the ADP1073, simply connect the feedback pin (Pin
8) directly to the output voltage.
The ADP1073 oscillator only turns on when the output voltage
is below the programmed voltage. When the output voltage is
above the programmed voltage, the ADP1073 remains in its
quiescent state to conserve power. Output ripple, which is in-
herent in gated oscillator converters, is typically 125 mV for a
5 V output and 300 mV for a 12 V output. This ripple voltage
can be greatly reduced by inserting the gain-block between the
output and the FB pin. Further information and a typical circuit
are shown in the Programming the Gain Block section.


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