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ADN2850ACP25 Datasheet(PDF) 9 Page - Analog Devices |
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ADN2850ACP25 Datasheet(HTML) 9 Page - Analog Devices |
9 / 20 page REV. B ADN2850 –9– Using Additional Internal Nonvolatile EEMEM The ADN2850 contains additional internal user storage registers (EEMEM) for saving constants and other 16-bit data. Table V provides an address map of the internal storage registers shown in the functional block diagram as EEMEM1, EEMEM2, and and 26 bytes (13 addresses 2 bytes each) of USER EEMEM. Table V. EEMEM Address Map EEMEM Number Address EEMEM Content For 1 0000 RDAC1 1, 2 2 0001 RDAC2 3 0010 USER1 3 4 0011 USER2 :: : 15 1110 USER13 16 1111 % Tolerance 4 NOTES 1RDAC data stored in EEMEM locations are transferred to their corresponding RDAC REGISTER at power-on, or when instructions 1, 8, and PR are executed. 2Execution of instruction 1 leaves the device in the read mode power consumption state. After the last instruction 1 is executed, the user should perform a NOP, instruction 0 to return the device to the low power idling state. 3USER <data> are internal nonvolatile EEMEM registers available to store and retrieve constants and other 16-bit information using instructions 3 and 9 respectively. 4Read only. Calculating Actual Full-Scale Resistance The actual tolerance of the rated full-scale resistance RWB1 is stored in EEMEM register 15 during factory testing. The actual full-scale resistance can therefore be calculated, which will be valuable for tolerance matching or calibration. Notice this value is read only, and the full-scale resistance of RWB2_FS matches RWB1_FS, of typically 0.1%. The tolerance in % is stored in the last 16 bits of data in EEMEM register 15. The format is sign magnitude binary format with the MSB designates for sign (0 = positive and 1 = negative), the next 7 MSB designate for the integer number, and the 8 LSB designate for the decimal number. See Table VI. Table VI. Tolerance in % from Rated Full-Scale Resistance For example, if RWB_FS_RATED = 250 k Ω and the data is 0001 1100 0000 1111, RWB_FS_ACTUAL can be calculated as follows: MSB: 0 = Positive Next 7 MSB: 001 1100 = 28 8 LSB: 0000 1111 = 15 2 –8 = 0.06 % Tolerance = +28.06% Thus, RWB_FS_ACTUAL = 320.15 k Ω Bit sign mag D15 sign D14 26 D13 25 D12 24 D11 23 D10 22 D9 21 D8 20 D7 2-1 D6 2-2 D5 2-3 D4 2-4 D3 2-5 D2 2-6 D1 2-7 D0 2-8 • Sign 7 Bits for Integer Number Decimal Point 8 Bits for Decimal Number conditions. Table IV illustrates the operation of the shifting function on the individual RDAC register data bits. Each line going down the table represents a successive shift operation. Note that the left shift 12 and 13 commands were modified such that if the data in the RDAC register is equal to zero, and the data is left shifted, the RDAC register is then set to code 1. Similarly, if the data in the RDAC register is greater than or equal to midscale, and the data is left shifted, then the data in the RDAC register is automatically set to full scale. This makes the left shift function as ideal a logarithmic adjustment as possible. The right shift 4 and 5 commands will be ideal only if the LSB is zero (i.e., ideal logarithmic—no error). If the LSB is a one, then the right shift function generates a linear half LSB error, which translates to a number of bits-dependent logarithmic error as shown in Figure 3. The plot shows the error of the odd numbers of bits for ADN2850. Table IV. Detail Left and Right Shift Functions for 6 dB Step Increment and Decrement Left Shift Right Shift 00 0000 0000 11 1111 1111 00 0000 0001 01 1111 1111 00 0000 0010 00 1111 1111 00 0000 0100 00 0111 1111 00 0000 1000 00 0011 1111 00 0001 0000 00 0001 1111 00 0010 0000 00 0000 1111 00 0100 0000 00 0000 0111 00 1000 0000 00 0000 0011 01 0000 0000 00 0000 0001 10 0000 0000 00 0000 0000 11 1111 1111 00 0000 0000 11 1111 1111 00 0000 0000 Actual conformance to a logarithmic curve between the data con- tents in the RDAC register and the wiper position for each right shift 4 and 5 command execution contains an error only for odd numbers of bits. Even numbers of bits are ideal. The graph in Figure 3 shows plots of Log_Error [i.e., 20 log10 (error/code)] ADN2850. For example, code 3 Log_Error = 20 log10 (0.5/3) = –15.56 dB, which is the worst case. The plot of Log_Error is more significant at the lower codes. CODE – From 1 to 1023 by 2.0 103 0 0 –20 –40 –60 –80 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 Figure 3. Plot of Log_Error Conformance for Odd Numbers of Bits Only (Even Numbers of Bits Are Ideal) Right Shift –6 dB/step Left Shift 6 dB/step |
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