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ADN2809 Datasheet(PDF) 1 Page - Analog Devices

Part No. ADN2809
Description  Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com

ADN2809 Datasheet(HTML) 1 Page - Analog Devices

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REV. PrB Sept 2001
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106,
Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
©Analog Devices, Inc., 2001
Multi-Rate to 2.7Gbps Clock and Data
Recovery IC with Limiting Amplifier
Preliminary Technical Data
Meets SONET Requirements for Jitter Transfer /
Generation / Tolerance
Quantizer Sensitivity: 6 mV typical
Adjustable Slice Level: +/- 100 mV
1.9GHz minimum Bandwidth
Loss of Signal Detect Range: 4mV to 17mV
Single Reference Clock Frequency for all rates
Including 15/14 (7%) Wrapper Rate
Choice of 19.44, 38.88, 77.76 or
inputs (LVPECL / LVDS only at 155.52 MHz)
19.44MHz Crystal Oscillator for Module apps
Loss of Lock indicator
Loopback mode for High Speed Test Data
Output Squelch & Clock Recovery Functions
Single Supply Operation: 3.3 Volts (+10%)
Low Power: 780 mW Typical
Patented Clock Recovery Architecture
7 x 7 mm 48 pin LFCSP
SONET OC-3/12/48, SDH STM-1/4/16, and all
associated FEC rates
WDM transponders
SONET/SDH regenerators and test equipment
Backplane applications
The ADN2809 provides the receiver functions of Quantization,
Signal Level Detect and Clock and Data Recovery at rates of
OC-3, OC-12, Gigabit Ethernet, OC-48 and all FEC rates. All
SONET jitter requirements are met, including: Jitter Transfer;
Jitter Generation; and Jitter Tolerance. All specifications are
quoted for -40 to 85C ambient temperature unless otherwise
The device is intended for WDM system applications and can be
used with either an external reference clock or an on-chip
oscillator crystal. Both native rates and 15/14 rate digital
‘wrappers’ rates are supported by the ADN2809, without any
change of reference clock required.
This device together with a PIN diode and a TIA preamplifier
can implement a highly integrated, low cost, low power fiber
optic receiver.
The receiver front end Signal Detect circuit indicates when the
input signal level has fallen below a user adjustable threshold.
The ADN2809 is available in a compact 48 pin chip scale
Functional Block Diagr am
Loss of lock

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