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ADMCF340-EVALKIT Datasheet(PDF) 26 Page - Analog Devices |
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ADMCF340-EVALKIT Datasheet(HTML) 26 Page - Analog Devices |
26 / 40 page REV. 0 ADMCF340 –26– Also SPORT1 Flag signal (FL1) is externally available through the FL1/DT1 Pin. This signal is used to drive the external serial memory input reset. With SPORT1 configured in UART Mode, the SPORT0 serial clock (SCLK0) is externally available through the SCLK1/ SCLK0 Pin. The SPORT1 data transmit (DT1) is externally available through the FL1/DT1 Pin. SPORT0 Configuration SPORT0 can be configured in the following modes: SPORT Mode UART Mode SPI Mode SPORT0 can be configured for UART Mode. In this mode, the DR0 and RFS0 signals of the internal serial port are connected together. DSP CORE SPORT1 DT1 FL1 TFS1 RFS1 DR1 SCLK1 DSP CORE SPORT0 SCLK0 DT0 DR0 TFS0 RFS0 SPI CONTROL BLOCK MODECTRL REGISTER (04) SPORT1 BOOT MODE/UART MODE MODECTRL REGISTER (15) SPORT0 SPORT MODE/UART MODE MODECTRL REGISTER (14..13..12) SPORT0 SPI INTERFACE CONTROL DT1/FL1 DR1 SCLK1/SCLK0 DT0 DR0 TFS0 RFS0 ADMCF340 Figure 18. SPORT0 and SPORT1 Internal Multiplexing (Simplied Diagram) SPORT0 can be configured to operate as master SPI interface. The SPI Mode is set through Bit 14 of MODECTRL Register. When SPORT0 is configured as SPI interface, the SPORT I/O pins assume the configuration shown in Table XI. The Slave Select Pin automatically generates the select signal at each word transfer. This pin can also be used as a general purpose I/O during the SPI transfer without affecting the SPORT operations. The SPI clock polarity and phase are configurable through Bits 13 and 12 of MODECTRL Register. The SPI transfer using clock phase is shown in Figure 19 and Figure 20. |
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