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ADMC328TR-XXX-YY Datasheet(PDF) 12 Page - Analog Devices |
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ADMC328TR-XXX-YY Datasheet(HTML) 12 Page - Analog Devices |
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12 / 32 page  ADMC328 –12– REV. B Three-Phase Timing Unit The 16-bit three-phase timing unit is the core of the PWM con- troller and produces three pairs of pulsewidth modulated signals with high resolution and minimal processor overhead. There are four main configuration registers (PWMTM, PWMDT, PWMPD and PWMSYNCWT) that determine the fundamental charac- teristics of the PWM outputs. In addition, the operating mode of the PWM (single or double update mode) is selected by Bit 6 of the MODECTRL register. These registers, in conjunction with the three 16-bit duty cycle registers (PWMCHA, PWMCHB and PWMCHC), control the output of the three-phase timing unit. PWM Switching Frequency: PWMTM Register The PWM switching frequency is controlled by the PWM period register, PWMTM. The fundamental timing unit of the PWM controller is tCK = 1/fCLKOUT where fCLKOUT is the CLKOUT frequency (DSP instruction rate). Therefore, for a 20 MHz CLKOUT, the fundamental time increment is 50 ns. The value written to the PWMTM register is effectively the number of tCK clock increments in half a PWM period. The required PWMTM value is a function of the desired PWM switching frequency (fPWM) and is given by: PWMTM f f f f CLKOUT PWM CLKIN PWM = × = 2 Therefore, the PWM switching period, TS, can be written as: T PWMTM t SCK =× × 2 For example, for a 20 MHz CLKOUT and a desired PWM switching frequency of 10 kHz (TS = 100 µs), the correct value to load into the PWMTM register is: PWMTM x E = × ×× = 20 10 21010 1000 0 3 8 6 3 The largest value that can be written to the 16-bit PWMTM register is 0xFFFF = 65,535, which corresponds to a minimum PWM switching frequency of: fHz PWM,min , = × × = 20 10 2 65 535 153 6 for a CLKOUT frequency of 20 MHz. PWM Switching Dead Time: PWMDT Register The second important PWM block parameter that must be initialized is the switching dead time. This is a short delay time introduced between turning off one PWM signal (for example AH) and turning on its complementary signal, AL. This short time delay is introduced to permit the power switch being turned off to completely recover its blocking capability before the complementary switch is turned on. This time delay prevents a potentially destructive short-circuit condition from developing across the dc link capacitor of a typical voltage source inverter. Dead time is controlled by the PWMDT register. The dead time is inserted into the three pairs of PWM output signals. The dead time, TD, is related to the value in the PWMDT register by: T PWMDT t PWMDT f DCK CLKOUT =× × = × 22 Therefore, a PWMDT value of 0x00A (= 10), introduces a 1 µs delay between the turn-off of any PWM signal (for example AH) and the turn-on of its complementary signal (AL). The amount of the dead time can therefore be programmed in increments of 2 tCK (or 100 ns for a 20 MHz CLKOUT). The PWMDT register is a 10-bit register. For a CLKOUT rate of 20 MHz its maximum value of 0x3FF (= 1023) corresponds to a maximum programmed dead time of: TDmax = 1023 × 2 × tCK = 1023 × 2 × 50 × 10–9 sec = 102 µs The dead time can be programmed to zero by writing 0 to the PWMDT register. PWM Operating Mode: MODECTRL and SYSSTAT Registers The PWM controller of the ADMCF328 can operate in two dis- tinct modes: single update mode and double update mode. The operating mode of the PWM controller is determined by the state of Bit 6 of the MODECTRL register. If this bit is cleared, the PWM operates in the single update mode. Setting Bit 6 places the PWM in the double update mode. By default, following either a peripheral reset or power-on, Bit 6 of the MODECTRL register is cleared. This means that the default operating mode is single update mode. In single update mode, a single PWMSYNC pulse is produced in each PWM period. The rising edge of this signal marks the start of a new PWM cycle and is used to latch new values from the PWM configuration registers (PWMTM, PWMDT, PWMPD and PWMSYNCWT) and the PWM duty cycle registers (PWMCHA, PWMCHB and PWMCHC) into the three-phase timing unit. The PWMSEG register is also latched into the output control unit on the rising edge of the PWMSYNC pulse. In effect, this means that the parameters of the PWM signals can be updated only once per PWM period at the start of each cycle. Thus, the generated PWM patterns are symmetrical about the midpoint of the switching period. In double update mode, there is an additional PWMSYNC pulse produced at the midpoint of each PWM period. The rising edge of this new PWMSYNC pulse is again used to latch new values of the PWM configuration registers, duty cycle registers and the PWMSEG register. As a result, it is possible to alter both the characteristics (switching frequency, dead time, minimum pulse- width and PWMSYNC pulsewidth) and the output duty cycles at the midpoint of each PWM cycle. Consequently, it is pos- sible to produce PWM switching patterns that are no longer symmetrical about the midpoint of the period (asymmetrical PWM patterns). In the double update mode, operation in the first half or the second half of the PWM cycle is indicated by Bit 3 of the SYSSTAT register. In double update mode, this bit is cleared during operation in the first half of each PWM period (between the rising edge of the original PWMSYNC pulse and the rising edge of the new PWMSYNC pulse, which is introduced in double update mode). Bit 3 of the SYSSTAT register is set during the second half of each PWM period. If required, a user may determine the status of this bit during a PWMSYNC inter- rupt service routine. The advantages of the double update mode are that lower har- monic voltages can be produced by the PWM process and wider control bandwidths are possible. However, for a given PWM switching frequency, the PWMSYNC pulses occur at twice the rate in the double update mode. Because new duty cycle values must be computed in each PWMSYNC interrupt service routine, there is a larger computational burden on the DSP in the double update mode. |
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