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ADM8693ARU Datasheet(PDF) 11 Page - Analog Devices

Part No. ADM8693ARU
Description  Microprocessor Supervisory Circuits
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ADM8693ARU Datasheet(HTML) 11 Page - Analog Devices

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ADM8690–ADM8695
REV. 0
–11–
TYPICAL APPLICATIONS
ADM8690, ADM8692 and ADM8694
Figure 22a shows the ADM8690/ADM8692/ADM8694 in a
typical power monitoring, battery backup application. VOUT
powers the CMOS RAM. Under normal operating conditions
with VCC present, VOUT is internally connected to VCC. If a
power failure occurs, VCC will decay and VOUT will be switched
to VBATT thereby maintaining power for the CMOS RAM. A
RESET pulse is also generated when VCC falls below 4.65 V for
the ADM8690/ADM8694 or 4.4 V for the ADM8692.
RESET
will remain low for 50 ms (200 ms for ADM8694) after VCC re-
turns to 5 V.
The watchdog timer input (WDI) monitors an I/O line from the
µP system. This line must be toggled once every 1.6 seconds to
verify correct software execution. Failure to toggle the line indi-
cates that the
µP system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
If the watchdog timer is not needed, the WDI input should be
left floating.
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network. The voltage on the PFI input is com-
pared with a precision 1.3 V internal reference. If the input volt-
age drops below 1.3 V, a power fail output (
PFO) signal is
generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold
voltage VT.
VT = (1.3 R1/R2) + 1.3 V
R1/R2 = (VT/1.3) – 1
+
BATTERY
R1
R2
+5V
0.1µF
ADM8690
ADM8692
ADM8694
VCC
PFI
VBATT
VOUT
WDI
PFO
RESET
GND
µP POWER
CMOS RAM
POWER
µP SYSTEM
µP
RESET
µP NMI
I/O LINE
Figure 22a. ADM8690/ADM8692/ADM8694 Typical Applica-
tion Circuit A
Figure 22b shows a similar application but in this case the PFI
input monitors the unregulated input to the 7805 voltage regu-
lator. This gives an earlier warning of an impending power fail-
ure. It is useful with processors operating at low speeds or where
there are a significant number of housekeeping tasks to be com-
pleted before the power is lost.
+
BATTERY
R1
R2
INPUT
POWER
V > 8V
0.1µF
0.1µF
7805
+5V
µP POWER
CMOS RAM
POWER
µP SYSTEM
µP
RESET
µP NMI
I/O LINE
ADM8690
ADM8692
ADM8694
VCC
PFI
VBATT
VOUT
WDI
PFO
RESET
GND
Figure 22b. ADM8690/ADM8692/ADM8694 Typical Applica-
tion Circuit B
ADM8691, ADM8693 and ADM8695
A typical connection for the ADM8691/ADM8693/ADM8695
is shown in Figure 23. CMOS RAM is powered from VOUT.
When 5 V power is present this is routed to VOUT. If VCC fails
then VBATT is routed to VOUT. VOUT can supply up to 100 mA
from VCC, but if more current is required, an external PNP tran-
sistor can be added. When VCC is higher than VBATT, the BATT
ON output goes low, providing up to 25 mA of base drive for
the external transistor. A 0.1
µF capacitor is connected to V
OUT
to supply the transient currents for CMOS RAM. When VCC is
lower than VBATT, an internal 20
Ω MOSFET connects the
backup battery to VOUT.
3V
BATTERY
R1
R2
0.1µF
0.1µF
0.1µF
RESET
SYSTEM STATUS
INDICATORS
NC
INPUT POWER
+5V
A0–A15
I/O LINE
NMI
RESET
µP
ADM8691
ADM8693
ADM8695
BATT
ON
VCC
VOUT
VBATT
CEOUT
CEIN
PFI
GND
OSC IN
OSC SEL
WDI
PFO
RESET
LOW LINE
WDO
ADDRESS
DECODE
CMOS
RAM
Figure 23. ADM8691/ADM8693/ADM8695 Typical
Application


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