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ADMC326YN Datasheet(PDF) 30 Page - Analog Devices |
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ADMC326YN Datasheet(HTML) 30 Page - Analog Devices |
30 / 31 page ADMC326 –30– REV. A SPORT1 RECEIVE OR IRQ0 IFC INTERRUPT FORCE INTERRUPT CLEAR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMER SOFTWARE 0 SOFTWARE 1 IRQ2 TIMER SOFTWARE 0 IRQ2 DSP REGISTER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPORT1 TRANSMIT OR IRQ1 SPORT1 RECEIVE OR IRQ0 SPORT1 TRANSMIT OR IRQ1 0 0 0 0 0 IRQ0 SENSITIVITY 0 = LEVEL 1 = EDGE ICNTL IRQ1 SENSITIVITY IRQ2 SENSITIVITY INTERRUPT NESTING 0 = DISABLE 1 = ENABLE DSP REGISTER 432 1 0 IMASK (R/W) PERIPHERAL (OR IRQ2) TIMER SPORT1 RECEIVE (OR IRQ0) SPORT1 TRANSMIT (OR IRQ1) SOFTWARE 0 SOFTWARE 1 0 0 0 0 0 0 0 00 0 0 00 0 0 0 DSP REGISTER 0 = DISABLE (MASK) 1 = ENABLE 0 = DISABLE (MASK) 1 = ENABLE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SOFTWARE 1 Figure 26. Configuration of Interrupt Control Registers Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these bits should always be written as shown. |
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