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ADM9240 Datasheet(PDF) 5 Page - Analog Devices

Part No. ADM9240
Description  Low Cost Microprocessor System Hardware Monitor
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADM9240 Datasheet(HTML) 5 Page - Analog Devices

 
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ADM9240
–5–
REV. 0
PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Description
1
NTEST_OUT/A0
Digital I/O. Dual Function Pin. The lowest order programmable bit of the Serial Bus Address.
This pin functions as an output when doing a NAND Tree test.
2
A1
Digital Input. The highest order programmable bit of the Serial Bus Address.
3
SDA
Digital I/O. Serial Bus Bidirectional Data. Open-drain output.
4
SCL
Digital Input. Serial Bus Clock.
5
FAN1
Digital Input. 0 to VCC amplitude fan tachometer input.
6
FAN2
Digital Input. 0 to VCC amplitude fan tachometer input.
7
CI
Digital I/O. An active high input from an external circuit that latches a Chassis Intrusion
event. This line can go high without any clamping action regardless of the powered state of
the ADM9240. The ADM9240 provides an internal open drain on this line, controlled by
Bit 6 of Register 40h or Bit 7 of Register 46h, to provide a minimum 20 ms pulse on this line,
to reset the external Chassis Intrusion Latch.
8
GNDD
Digital Ground. Internally connected to all of the digital circuitry.
9VCC
Power (+2.85 V to +5.75 V). Typically powered from +3.3 V or +5 V power rail. Bypass with
the parallel combination of 10
µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass
capacitors.
10
INT
Digital Output. Interrupt Request (open drain). The output is enabled when Bit 1 of the
Configuration Register is set to 1. The default state is disabled.
11
NTEST_IN/AOUT
Digital Input/Analog Output. An active-high input that enables NAND Tree mode board-
level connectivity testing. Refer to section on NAND Tree testing. Also functions as a pro-
grammable analog output when NAND Tree is not selected
12
RESET
Digital I/O. Master Reset, 5 mA driver (open drain), active low output with a 20 ms minimum
pulsewidth. Available when enabled via Bit 7 in Register 44h, and set using Bit 4 in Register
40h. Also acts as reset input when pulled low (e.g., power-on reset).
13
GNDA
Analog Ground. Internally connected to all analog circuitry. The ground reference for all
analog inputs.
14
+VCCP2
Analog Input. Monitors processor core voltage +VCCP2 (0 V–3.6 V). Can also be used to
monitor the –12 V supply by adding two external resistors.
15
+12 VIN
Analog Input. Monitors +12 V supply.
16
+5 VIN
Analog Input. Monitors +5 V supply.
17
+3.3 VIN
Analog Input. Monitors +3.3 V supply.
18
+2.5 VIN
Analog Input. Monitors +2.5 V supply.
19
+VCCP1
Analog Input. Monitors processor core voltage +VCCP1 (0 V–3.6 V).
20
VID4
Digital Input. Core Voltage ID readouts from the processor. This value is read into the
VID4 Status Register.
21
VID3
Digital Input. Core Voltage ID readouts from the processor. This value is read into the
VID0–VID3 Status Register.
22
VID2
Digital Input. Core Voltage ID readouts from the processor. This value is read into the
VID0–VID3 Status Register.
23
VID1
Digital Input. Core Voltage ID readouts from the processor. This value is read into the
VID0–VID3 Status Register.
24
VID0
Digital Input. Core Voltage ID readouts from the processor. This value is read into the
VID0–VID3 Status Register.


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