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ADM8690AN Datasheet(PDF) 4 Page - Analog Devices

Part No. ADM8690AN
Description  Microprocessor Supervisory Circuits
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ADM8690AN Datasheet(HTML) 4 Page - Analog Devices

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REV. 0
Power Supply Input: +5 V Nominal.
Backup Battery Input.
Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest potential. VOUT
can supply up to 100 mA to power CMOS RAM. Connect VOUT to VCC if VOUT and VBATT are not used.
0 V. Ground reference for all signals.
Logic Output.
RESET goes low if
1. VCC falls below the Reset Threshold
2. The watchdog timer is not serviced within its timeout period.
The reset threshold is typically 4.65 V for the ADM8690/ADM8691/ADM8694/ADM8695 and 4.4 V for the ADM8692
and ADM8693.
RESET remains low for 50 ms (ADM8690/ADM8691/ADM8692/ADM8693) or 200 ms (ADM8694/
ADM8695) after VCC returns above the threshold. RESET also goes low for 50 (200) ms if the watchdog timer is
enabled but not serviced within its timeout period. The
RESET pulse width can be adjusted on the ADM8691/ADM8693/
ADM8695 as shown in Table I. The
RESET output has an internal 3
µA pull up, and can either connect
to an open collector Reset bus or directly drive a CMOS gate without an external pull-up resistor.
Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watchdog timeout
RESET pulses low and WDO goes low. The timer resets with each transition on the WDI line. The watchdog
timer may be disabled if WDI is left floating or is driven to midsupply.
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is less than 1.3 V,
goes low. Connect PFI to GND or VOUT when not used.
Power Fail Output.
PFO is the output of the Power Fail Comparator. It goes low when PFI is less than 1.3 V. The
comparator is turned off and
PFO goes low when VCC is below VBATT.
Logic Input. The input to the
CE gating circuit. Connect to GND or VOUT if not used.
Logic Output.
CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when VCC is above the reset
threshold. If VCC is below the reset threshold, CEOUT is forced high. See Figures 5 and 6.
Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when VOUT
is internally switched to VCC. The output typically sinks 35 mA and can directly drive the base of an external
PNP transistor to increase the output current above the 100 mA rating of VOUT.
Logic Output.
LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as VCC rises
above the reset threshold.
Logic Output. RESET is an active high output. It is the inverse of
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscillator sets
the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator input, OSC IN,
is enabled. OSC SEL has a 3
µA internal pull-up (see Table I).
Oscillator Logic Input. With OSC SEL low, OSC IN can be driven by an external clock signal or an external
capacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the watch-
dog timeout period (see Table I and Figure 4). With OSC SEL high or floating, the internal oscillator is enabled
and the reset active time is fixed at 50 ms typ. (ADM8691/ADM8693) or 200 ms typ (ADM8695). In this mode the
OSC IN pin selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. In both modes, the timeout
period immediately after a reset is 1.6 s typical.
Logic Output. The Watchdog Output,
WDO, goes low if WDI remains either high or low for longer than the
watchdog timeout period.
WDO is set high by the next transition at WDI. If WDI is unconnected or at midsupply,
the watchdog timer is disabled and
WDO remains high. WDO also goes high when LOW LINE goes low.

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