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ADM698 Datasheet(PDF) 4 Page - Analog Devices

Part No. ADM698
Description  Microprocessor Supervisory Circuits
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ADM698 Datasheet(HTML) 4 Page - Analog Devices

   
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ADM698/ADM699
REV. 0
–4–
CIRCUIT INFORMATION
Power Fail RESET
A precision voltage detector monitors VCC and generates a
RESET
output to hold the microprocessor’s Reset line low when
VCC falls below the reset threshold (4.65 V) (see Figure 4). The
reset voltage threshold is set to accommodate a 5% variation on
VCC. The voltage detector has 40 mV hysteresis to ensure that
glitches on VCC do not activate the RESET output.
On power up, an internal monostable holds RESET low for
140 ms after VCC rises above the reset threshold. This allows the
power supply to stabilize on power up and also prevents re-
peated toggling of RESET even if the 5 V power drops out and
recovers with each power line cycle. In order to prevent
mistriggering due to transient voltage spikes, it is recommended
that a 0.1
µF capacitor be connected at the V
CC pin.
The RESET output is guaranteed to remain low with VCC as
low as 1 V. This holds the microprocessor in a stable shutdown
condition as the power supply comes up.
On the 16-lead SOIC package, an active high RESET output is
also provided. This is the complement of RESET and is in-
tended for microprocessors requiring an active high signal.
V2
V2
V1
V1
VCC
RESET
V1 = RESET VOLTAGE THRESHOLD
V2 = RESET VOLTAGE THRESHOLD +
THRESHOLD HYSTERESIS
t
1 = RESET TIME
t
1
t
1
Figure 4. Watchdog Timeout Period vs. Temperature
Watchdog Timer (ADM699 Only)
The watchdog timer input (WDI) monitors an I/O line from the
µP system. The µP must toggle this input once every 1.6 sec-
onds to verify correct software execution. Failure to toggle the
line indicates that the
µP system is not correctly executing its
program and may be tied up in an endless loop. If this happens,
a reset pulse is generated to initialize the processor.
The WDI input is a three level input and will recognize a low
to- high or a high-to-low transition on its input. The watchdog
timer is reset by each WDI transition and then begins its
timeout period. If the WDI pin remains either high or low, reset
pulses will be issued every 1.6 seconds typically. If the watch-
dog timer is not needed, the WDI input should be left floating.
The Watchdog Output (WDO) (SOIC package Only) provides
watchdog status information. It is driven low if WDI is not
toggled within the watchdog timeout period. It goes high at the
next WDI transition. It is also set high when VCC falls below the
reset threshold.
t1 = RESET TIME
t2 = WATCHDOG TIME OUT PERIOD
t1
t1
WDI
RESET
t1
WDO
t2
t2
Figure 5. Watchdog Timeout Period and Reset Active Time
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Pin Cerdip
(Q-8)
PIN 1
0.420 (10.67)
MAX
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.310 (7.87)
0.220 (5.59)
0.200
(5.08)
MAX
PLANE
SEATING
0.070 (1.78)
0.30 (0.76)
0.100 (2.54)
BSC
0.022 (0.558)
0.014 (0.356)
1
4
5
8
0.015 (0.381)
0.008 (0.204)
0.320 (8.13)
0.290 (7.37)
16-Lead SOIC
(R-16)
0.019 (0.49)
0.05 (1.27)
REF
0.104
(2.65)
0.012
(0.3)
0.413 (10.50)
0.419
(10.65)
0.299
(7.60)
1
8
9
16
0.042
(1.07)
0.013
(0.32)
0.030
(0.75)
8-Pin Plastic DIP
(N-8)


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