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ADM696 Datasheet(PDF) 4 Page - Analog Devices

Part No. ADM696
Description  Microprocessor Supervisory Circuits
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ADM696 Datasheet(HTML) 4 Page - Analog Devices

 
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ADM696/ADM697
REV. 0
–4–
PIN FUNCTION DESCRIPTION
Pin No.
Mnemonic
ADM696
ADM697
Function
VCC
3
3
Power Supply Input +3 V to +5 V.
VBATT
1
Backup Battery Input. Connect to Ground if a backup battery is not used.
VOUT
2
Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the
highest potential. VOUT can supply up to 100 mA to power CMOS RAM. Connect VOUT to
VCC if VOUT and VBATT are not used.
GND
4
5
0 V. Ground reference for all signals.
RESET
15
15
Logic Output. RESET goes low whenever LLIN falls below 1.3 V or when VCC falls below
the VBATT input voltage. RESET remains low for 50 ms after LLIN goes above 1.3 V,
RESET
also goes low for 50 ms if the watchdog timer is enabled but not serviced within its
timeout period. The RESET pulse width can be adjusted as shown in Table I.
WDI
11
11
Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer
than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets
with each transition at the WDI input. The watchdog timer is disabled when WDI is left
floating or is driven to midsupply.
PFI
9
9
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is
less than 1.3 V, PFO goes low. Connect PFI to GND or VOUT when not used. See Figure 1.
PFO
10
10
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI
is less than 1.3 V. The comparator is turned off and PFO goes low when VCC is below
VBATT.
CEIN
13
Logic Input. The input to the CE gating circuit. Connect to GND or VOUT if not used.
CEOUT
12
Logic Output. CEOUT is a gated version of the CEIN signal. CEOUT tracks CEIN when LLIN
is above 1.3 V. If LLIN is below 1.3 V, CEOUT is forced high.
BATT ON
5
Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input.
It goes low when VOUT is internally switched to VCC. The output typically sinks 7 mA and
can directly drive the base of an external PNP transistor to increase the output current above
the 100 mA rating of VOUT.
LOW LINE
6
6
Logic Output. LOW LINE goes low when LLIN falls below 1.3 V. It returns high as soon as
LLIN rises above 1.3 V.
RESET
16
16
Logic Output. RESET is an active high output. It is the inverse of RESET.
OSC SEL
8
8
Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal
oscillator sets the reset time delay and watchdog time-out period. When OSC SEL is low,
the external oscillator input, OSC IN, is enabled. OSC SEL has a 3
µA internal pullup. See
Table I and Figure 4.
OSC IN
7
7
Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock
to adjust both the reset delay and the watchdog time-out period. The timing can also be
adjusted by connecting an external capacitor to this pin. See Table I and Figure 4. When
OSC SEL is high or floating, OSC IN selects between fast and slow watchdog time-out periods.
WDO
14
14
Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low
for longer than the watchdog time-out period. WDO is set high by the next transition at
WDI. If WDI is unconnected or at midsupply, WDO remains high. WDO also goes high
when LOW LINE goes low.
NC
12
2
No Connect. It should be left open.
LLIN
13
4
Voltage Sensing Input. The voltage on the low line input, LLIN, is compared with a 1.3 V
reference voltage. This input is normally used to monitor the power supply voltage. The
output of the comparator generates a LOW LINE output signal. It also generates a
RESET/RESET output.
TEST
1
This is a special test pin using during device manufacture. It should be connected to GND.


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