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ADM696 Datasheet(PDF) 6 Page - Analog Devices

Part No. ADM696
Description  Microprocessor Supervisory Circuits
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADM696 Datasheet(HTML) 6 Page - Analog Devices

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ADM696/ADM697
REV. 0
–6–
Table I. ADM696, ADM697 Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period
Reset Active Period
OSC SEL
OSC IN
Normal
Immediately After Reset
Low
External Clock Input
1024 CLKS
4096 CLKS
512 CLKS
Low
External Capacitor
400 ms
× C/47 pF
1.6 s
× C/47 pF
200 ms
× C/47 pF
Floating or High
Low
100 ms
1.6 s
50 ms
Floating or High
Floating or High
1.6 s
1.6 s
50 ms
NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF).
t
2
RESET
WDO
WDI
t
1
= RESET TIME
t
2
= NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t
3
= WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
t
1
t
1
t
1
t
3
Figure 3. Watchdog Timeout Period and Reset Active Time
The watchdog timeout period defaults to 1.6 s and the reset
pulse width defaults to 50 ms but these times to be adjusted as
shown in Table I. Figure 4 shows the various oscillator configu-
rations which can be used to adjust the reset pulse width and
watchdog timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. In either case, immedi-
ately after a reset the timeout period is 1.6 s. This gives the mi-
croprocessor time to reinitialize the system. If OSC IN is low,
then the 100 ms watchdog period becomes effective after the
first transition of WDI. The software should be written such
that the I/O port driving WDI is left in its power-up reset state
until the initialization routines are completed and the micropro-
cessor is able to toggle WDI at the minimum watchdog timeout
period of 70 ms.
OSC IN
OSC SEL
ADM69x
CLOCK
0 TO 250kHz
8
7
Figure 4a. External Clock Source
OSC IN
OSC SEL
ADM69x
8
7
C
OSC
Figure 4b. External Capacitor
OSC IN
OSC SEL
ADM69x
8
7
NC
NC
Figure 4c. Internal Oscillator (1.6 s Watchdog)
OSC IN
OSC SEL
ADM69x
8
7
NC
Figure 4d. Internal Oscillator (100 ms Watchdog)
Watchdog Output (WDO)
The Watchdog Output WDO provides a status output which
goes low if the watchdog timer “times out” and remains low
until set high by the next transition on the watchdog input.
WDO
is also set high when LLIN goes below the reset threshold.


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