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ADM691A Datasheet(PDF) 4 Page - Analog Devices

Part No. ADM691A
Description  Microprocessor Supervisory Circuits
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ADM691A Datasheet(HTML) 4 Page - Analog Devices

 
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ADM691A/ADM693A/ADM800L/M
–4–
REV. 0
PIN DESCRIPTIONS
Pin
Mnemonic
Function
1VBATT
Backup Battery Input. Connect to external battery or capacitor. Connect to ground if a backup battery is
not used.
2VOUT
Output Voltage, VCC or VBATT is internally switched to VOUT depending on which is at the highest poten-
tial. When VCC is higher than VBATT and is also higher than the reset threshold, VCC is switched to VOUT.
When VCC is lower than VBATT and below the reset threshold, VBATT is switched to VOUT. Connect VOUT to
VCC if a backup battery is not being used.
3VCC
Power Supply Input; +5 V.
4
GND
0 V. Ground reference for all signals.
5
BATT ON
Logic Output. BATT ON goes high when VOUT is internally switched to the VBATT input. It goes low when
VOUT is internally switched to VCC. The output may also be used to drive the base (via a resistor) of an ex-
ternal PNP transistor to increase the output current above the 250 mA rating of VOUT.
6
LOW LINE
Logic Output. LOW LINE goes low when VCC falls below the reset threshold. It returns high as soon as
VCC rises above the reset threshold.
7
OSC IN
Oscillator Logic Input. With OSC SEL high or floating, the internal oscillator is enabled and sets the reset
delay and the watchdog timeout period. Connecting OSC IN low selects 100 ms while leaving it floating
selects 1.6 sec. With OSC SEL low, OSC IN can be driven by an external clock signal or an external ca-
pacitor can be connected between OSC IN and GND. This sets both the reset active pulse timing and the
watchdog timeout period. (See Table II and Figure 4.)
8
OSC SEL
Logic Oscillator Select Input. When OSC SEL is unconnected (floating) or driven high, the internal oscil-
lator sets the reset active time and watchdog timeout period. When OSC SEL is low, the external oscillator
input, OSC IN, is enabled. OSC SEL has a 10
µA internal pullup.
9
PFI
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator. When PFI is less than
1.25 V, PFO goes low. Connect PFI to GND or VOUT when not used.
10
PFO
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI is less than
1.25 V.
11
WDI
Watchdog Input. WDI is a three level input. If WDI remains either high or low for longer than the watch-
dog timeout period, RESET pulses low and WDO goes low. The timer resets with each transition on the
WDI line. The Watchdog Timer may be disabled if WDI is left floating or is driven to midsupply.
12
CEOUT
Output. CEOUT goes low only when CEIN is low and VCC is above the reset threshold. If CEIN is low when
reset is asserted, CEOUT will remain low for 15
µs or until CE
IN goes high, whichever occurs first.
13
CEIN
Chip Enable Input. The input to the CE gating circuit. Connect to GND or VOUT if not used.
14
WDO
Logic Output. The Watchdog Output, WDO, goes low if WDI remains either high or low for longer than
the Watchdog timeout period. WDO is set high by the next transition at WDI. WDO remains high if WDI
is unconnected.
15
RESET
Logic Output. RESET goes low if VCC falls below the Reset Threshold. It remains low for 200 ms typ after
VCC goes above the reset threshold.
16
RESET
Logic Output. RESET is an open-drain output. It is the inverse of RESET.
PIN CONFIGURATIONS
VBATT
CEIN
OSC IN
OSC SEL
BATT ON
LOW LINE
VOUT
CEOUT
RESET
RESET
PFO
WDI
VCC
WDO
GND
PFI
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
ADM691A
ADM693A
ADM800L
ADM800M


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