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ADM485AQ Datasheet(PDF) 2 Page - Analog Devices

Part No. ADM485AQ
Description  5 V Low Power EIA RS-485 Transceiver
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADM485AQ Datasheet(HTML) 2 Page - Analog Devices

   
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ADM485–SPECIFICATIONS
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
DRIVER
Differential Output Voltage, VOD
5.0
V
R =
∞, Figure 1
2.0
5.0
V
VCC = 5 V, R = 50
Ω (RS-422), Figure 1
1.5
5.0
V
R = 27
Ω (RS-485), Figure 1
VOD3
1.5
5.0
V
VTST = –7 V to +12 V, Figure 2
∆|V
OD| for Complementary Output States
0.2
V
R = 27
Ω or 50 Ω, Figure 1
Common-Mode Output Voltage VOC
3
V
R = 27
Ω or 50 Ω, Figure 1
∆|VOC| for Complementary Output States
0.2
V
R = 27
Ω or 50 Ω
Output Short Circuit Current (VOUT = High) 35
250
mA
–7 V
≤ V
O
≤ +12 V
Output Short Circuit Current (VOUT = Low)
35
250
mA
–7 V
≤ VO ≤ +12 V
CMOS Input Logic Threshold Low, VINL
0.8
V
CMOS Input Logic Threshold High, VINH
2.0
V
Logic Input Current (DE, DI)
±1.0
µA
RECEIVER
Differential Input Threshold Voltage, VTH
–0.2
+0.2
V
–7 V
≤ VCM ≤ +12 V
Input Voltage Hysteresis,
∆V
TH
70
mV
VCM = 0 V
Input Resistance
12
k
–7 V
≤ VCM ≤ +12 V
Input Current (A, B)
+1
mA
VIN = 12 V
–0.8
mA
VIN = –7 V
Logic Enable Input Current (
RE)
±1
µA
CMOS Output Voltage Low, VOL
0.4
V
IOUT = +4.0 mA
CMOS Output Voltage High, VOH
4.0
V
IOUT = –4.0 mA
Short Circuit Output Current
7
85
mA
VOUT = GND or VCC
Tristate Output Leakage Current
±1.0
µA
0.4 V
≤ VOUT ≤ +2.4 V
POWER SUPPLY CURRENT
ICC (Outputs Enabled)
1.35
2.2
mA
Outputs Unloaded, Digital Inputs = GND or VCC
ICC (Outputs Disabled)
0.7
1
mA
Outputs Unloaded, Digital Inputs = GND or VCC
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
DRIVER
Propagation Delay Input to Output TPLH, TPHL
210
15
ns
RL Diff = 54
Ω CL1 = CL2 = 100 pF, Figure 3
Driver O/P to
O/P T
SKEW
05
ns
RL Diff = 54
Ω C
L1 = CL2 = 100 pF, Figure 3
Driver Rise/Fall Time TR, TF
210
ns
RL Diff = 54
Ω CL1 = CL2 = 100 pF, Figure 3
Driver Enable to Output Valid
10
25
ns
Driver Disable Timing
10
25
ns
RECEIVER
Propagation Delay Input to Output TPLH, TPHL
18
25
40
ns
CL = 15 pF, Figure 5
Skew |TPLH–TPHL|0
5
ns
Receiver Enable TEN1
15
25
ns
Figure 6
Receiver Disable TEN2
15
25
ns
Figure 6
Specifications subject to change without notice.
REV. A
–2–
(VCC = +5 V
5%. All specifications TMIN to TMAX unless otherwise noted)
(VCC = +5 V
5%. All specifications TMIN to TMAX unless otherwise noted.)


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