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ADM1029 Datasheet(PDF) 2 Page - Analog Devices

Part No. ADM1029
Description  Dual PWM Fan Controller and Temperature Monitor for High Availability Systems
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADM1029 Datasheet(HTML) 2 Page - Analog Devices

 
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REV. 0
–2–
ADM1029–SPECIFICATIONS1, 2 (T
A = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY
Supply Voltage, VCC
3.0
3.30
5.5
V
Supply Current, ICC
1.7
3.0
mA
Interface Inactive, ADC Active
1.5
mA
ADC Inactive, DAC Active
10
60
µA
Shutdown Mode
TEMPERATURE-TO-DIGITAL CONVERTER
Internal Sensor Accuracy
± 1
±3
°C
Resolution
1
°C
External Diode Sensor Accuracy
± 3
±5
°C0°C ≤ T
A
≤ 100°C
Resolution
1
°C
Remote Sensor Source Current
90
µA
High Level
5.5
µA
Low Level
ANALOG-TO-DIGITAL CONVERTER
Total Unadjusted Error, TUE
±1
%
Note 3
Differential Nonlinearity, DNL
±1
LSB
Power Supply Sensitivity
± 1
%/ V
Conversion Time
Analog Input or Internal Temperature
11.6
ms
External Temperature
185.6
ms
FAN RPM-TO-DIGITAL CONVERTER
Accuracy
±6%
60
°C ≤ T
A
≤ 100°C: V
CC = 3.3 V
Full-Scale Count
255
FAN 1 and FAN 2 Nominal Input RPM
4
8800
rpm
Divisor = 1, Fan Count = 153
4400
rpm
Divisor = 2, Fan Count = 153
2200
rpm
Divisor = 4, Fan Count = 153
1100
rpm
Divisor = 8, Fan Count = 153
Internal Clock Frequency
56.4
60.0
63.6
kHz
OPEN-DRAIN DIGITAL OUTPUTS (
INT, CFAULT)
Output Low Voltage, VOL
0.4
V
IOUT = –6.0 mA, VCC = 3 V
High Level Output Current, IOH
0.1
1
µAV
OUT = VCC
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, VOL
0.4
V
IOUT = –6.0 mA, VCC = 3 V
High Level Output Leakage Current, IOH
0.1
1
µAV
OUT = VCC
SERIAL BUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
2.1
V
Input Low Voltage, VIL
0.8
V
Hysteresis
500
mV
DIGITAL INPUT LOGIC LEVELS
RESET,
GPIO1-6, FAULT1/2, TACH1/2, PRESENT1/2
Input High Voltage, VIH
2.1
V
Input Low Voltage, VIL
0.8
V
DIGITAL INPUT CURRENT
Input High Current, IIH
–1
µAV
IN = VCC
Input Low Current, IIL
+1
µAVIN = 0
Input Capacitance, CIN
20
pF
SERIAL BUS TIMING
5
Clock Frequency, fSCLK
10
100
kHz
See Figure 1
Glitch Immunity, tSW
50
ns
See Figure 1
Bus Free Time, tBUF
4.7
µs
See Figure 1
Start Setup Time, tSU:STA
4.7
µs
See Figure 1
Start Hold Time, tHD:STA
4
µs
See Figure 1
Stop Condition Setup Time, tSU:STO
4
µs
See Figure 1


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