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ADM1023 Datasheet(PDF) 2 Page - Analog Devices

Part No. ADM1023
Description  ACPI-Compliant High-Accuracy Microprocessor System Temperature Monitor
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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ADM1023 Datasheet(HTML) 2 Page - Analog Devices

 
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–2–
REV. A
ADM1023–SPECIFICATIONS (T
A = TMIN to TMAX
1, V
DD = 3.0 V to 3.6 V, unless otherwise noted)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER SUPPLY AND ADC
Temperature Resolution, Local Sensor
1
°C
Guaranteed No Missed Codes
Temperature Resolution, Remote Sensor
0.125
°C
Guaranteed No Missed Codes
Temperature Error, Local Sensor
–1.5
±0.5
+1.5
°CT
A = 60
°C to 100°C
–3
±1+3
°CTA = 0°C to 120°C
Temperature Error, Remote Sensor
–1
+1
°CTA, TD = 60°C to 100°C (Note 2)
–3
+3
°CT
A, TD = 0
°C to 120°C (Note 2)
Relative Accuracy
0.25
°CTA = 60°C to 100°C
Supply Voltage Range
3
3.6
V
Note 3
Undervoltage Lockout Threshold
2.55
2.7
2.8
V
VDD Input, Disables ADC, Rising Edge
Undervoltage Lockout Hysteresis
25
mV
Power-On Reset Threshold
0.9
1.7
2.2
V
VDD, Falling Edge (Note 4)
POR Threshold Hysteresis
50
mV
Standby Supply Current
1
5
µAVDD = 3.3 V, No SMBus Activity
4
µA
SCLK at 10 kHz
Average Operating Supply Current
130
200
µA
0.25 Conversions/Sec Rate
Autoconvert Mode, Averaged Over 4 Sec
225
330
µA
2 Conversions/Sec Rate
Conversion Time
65
115
170
ms
From Stop Bit to Conversion
Complete (Both Channels)
D+ Forced to D– + 0.65 V
Remote Sensor Source Current
120
205
300
µA
High Level (Note 4)
712
16
µA
Low Level (Note 4)
D-Source Voltage
0.7
V
Address Pin Bias Current (ADD0, ADD1)
50
µA
Momentary at Power-On Reset
SMBus INTERFACE
Logic Input High Voltage, VIH
2.2
V
VDD = 3 V to 5.5 V
STBY, SCLK, SDATA
Logic Input Low Voltage, VIL
0.8
V
VDD = 3 V to 5.5 V
STBY, SCLK, SDATA
SMBus Output Low Sink Current
6
mA
SDATA Forced to 0.6 V
ALERT Output Low Sink Current
1
mA
ALERT Forced to 0.4 V
Logic Input Current, IIH, IIL
–1
+1
µA
SMBus Input Capacitance, SCLK, SDATA
5
pF
SMBus Clock Frequency
100
kHz
SMBus Clock Low Time, tLOW
4.7
µst
LOW Between 10% Points
SMBus Clock High Time, tHIGH
4ns
tHIGH Between 90% Points
SMBus Start Condition Setup Time, tSU:STA
4.7
ns
SMBus Start Condition Hold Time, tHD:STA
4
ns
Time from 10% of SDATA to 90%
of SCLK
SMBus Stop Condition Setup Time, tSU:STO
4
ns
Time from 90% of SCLK to 10%
of SDATA
SMBus Data Valid to SCLK
250
ns
Time for 10% or 90% of
Rising Edge Time, tSU:DAT
SDATA to 10% of SCLK
SMBus Data Hold Time, tHD:DAT
0
µs
SMBus Bus Free Time, tBUF
4.7
µs
Between Start/Stop Condition
SCLK Falling Edge to SDATA
1
µs
Master Clocking in Data
Valid Time, tVD,DAT
SMBus Leakage Current
5
µAVDD = 0 V
NOTES
1T
MAX = 120
°C, T
MIN = 0
°C.
2T
D is temperature of remote thermal diode; T A, TD = 60
°C to 100°C.
3Operation at V
DD = 5 V guaranteed by design, not production tested.
4Guaranteed by design, not production tested.
Specifications subject to change without notice.


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