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ADM1022ARQ Datasheet(PDF) 3 Page - Analog Devices

Part # ADM1022ARQ
Description  Low-Cost PC Temperature Monitor and Fan Control ASIC
Download  19 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

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REV. 0
–3–
ADM1022
Parameter
Min
Typ
Max
Unit
Test Conditions
DIGITAL INPUT LOGIC LEVELS
(FAN_SPD/NTEST_IN,
ADD/NTEST_OUT,
MR, GPI)
Input High Voltage, VIH
2.2
V
Input Low Voltage, VIL
0.8
V
DIGITAL INPUT LEAKAGE CURRENT
(ALL DIGITAL INPUTS)
Input High Current, IIH
–1
–0.005
µAVIN = VCC
Input Low Current, IIL
+0.005
+1
µAVIN = 0
Input Capacitance, CIN
5pF
SERIAL BUS TIMING3
Clock Frequency, fSCLK
400
kHz
See Figure 1
Glitch Immunity, tSW
50
ns
See Figure 1
Bus Free Time, tBUF
1.3
µs
See Figure 1
Start Setup Time, tSU:STA
600
ns
See Figure 1
Start Hold Time, tHD:STA
600
ns
See Figure 1
Stop Condition Setup Time, tSU:STO
600
ns
See Figure 1
SCL Low Time, tLOW
1.3
µs
See Figure 1
SCL High Time, tHIGH
0.6
µs
See Figure 1
SCL, SDA Rise Time, tR
300
ns
See Figure 1
SCL, SDA Fall Time, tF
300
ns
See Figure 1
Data Setup Time, tSU:DAT
100
ns
See Figure 1
Data Hold Time, tHD:DAT
300
ns
See Figure 1
NOTES
1Typicals are at T
A = 25
°C and represent most likely parametric norm. Standby current typ is measured with V
CC = 3.3 V.
2ADD is a three-state input that may be pulled high, low or left open-circuit.
3Timing specifications are tested at logic levels of V
IL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge.
Specifications subject to change without notice.
P
S
P
tHD;STA
tSU;STA
tSU;DAT
tHIGH
tF
tHD;DAT
tR
tLOW
tHD;STA
tBUF
S
SCL
SDA
tSU;STO
Figure 1. Diagram for Serial Bus Timing


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