NCP1631

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Table 3. DETAILED PIN DESCRIPTION

Pin Number

Name

Function

1

ZCD2

This is the zero current detection pin for phase 2 of the interleaved PFC stage. Apply the voltage

from an auxiliary winding to detect the core reset of the inductor and the valley of the MOSFET

drain source voltage

2

FB

This pin receives a portion of the pre−converter output voltage. This information is used for the reg-

output voltage drops below 95.5% of the wished level.

3

The resistor placed between pin 3 and ground adjusts the maximum on−time of our system for both

phases, and hence the maximum power that can be delivered by the PFC stage.

4

OSC

Connect a capacitor to set the clamp frequency of the PFC stage. If wished, this frequency can be

reduced in light load as a function of the resistor placed between pin 6 and ground (frequency

fold−back). If the coil current cycle is longer than the selected switching period, the circuit delays

the next cycle until the core is reset. Hence, the PFC stage can operate in Critical Conduction Mode

in the most stressful conditions.

5

The error amplifier output is available on this pin. The capacitor connected between this pin and

ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power

Factor ratios.

Pin5 is grounded when the circuit is off so that when it starts operation, the power increases slowly

(soft−start).

6

Freq. Foldback

Apply a resistor between pin 6 and ground to adjust the oscillator charge current. Clamped not to

exceed 100 mA, this charge current is made proportional to the power level for a reduced switching

frequency at light load and an optimum efficiency over the load range.

7

BO

(Brown−out

Protection)

below 1 V. A 50−ms internal delay blanks short mains interruptions to help meet hold−up time re-

quirements. When it detects a brown−out condition, the circuit stops pulsing and grounds the

“pfcOK” pin to disable the downstream converter. Also an internal 7−mA current source is activated

to offer a programmable hysteresis.

The pin2 voltage is internally re−used for feed−forward.

Grounding pin 7 disables the part (after the 50−ms blanking time has elapsed).

8

OVP / UVP

voltage exceeds 2.5 V (OVP).

9

CS

This pin monitors a negative voltage proportional to the coil current. This signal is sensed to limit the

maximum coil current and protect the PFC stage in presence of in−rush currents.

10

Latch

Apply a voltage higher than 2.5 V to latch−off the circuit. The device is reset by unplugging the PFC

11

DRV2

This is the gate drive pin for phase 2 of the interleaved PFC stage. The high current capability of the

totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate charge power

MOSFETs.

12

to 20 V.

13

GND

Connect this pin to the pre−converter ground.

14

DRV1

This is the gate drive pin for phase 1 of the interleaved PFC stage. The high current capability of the

totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate charge power

MOSFETs.

15

REF5V /

pfcOK

The pin15 voltage is high (5 V) when the PFC stage is in a normal, steady state situation and low

otherwise. This signal serves to “inform” the downstream converter that the PFC stage is ready and

that hence, it can start operation.

16

ZCD1

This is the zero current detection pin for phase 1 of the interleaved PFC stage. Apply the voltage

from an auxiliary winding to detect the core reset of the inductor and the valley of the MOSFET

drain source voltage.