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NCP1631 Datasheet(PDF) 6 Page - ON Semiconductor |
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NCP1631 Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 23 page NCP1631 http://onsemi.com 6 Table 3. DETAILED PIN DESCRIPTION Pin Number Name Function 1 ZCD2 This is the zero current detection pin for phase 2 of the interleaved PFC stage. Apply the voltage from an auxiliary winding to detect the core reset of the inductor and the valley of the MOSFET drain source voltage 2 FB This pin receives a portion of the pre−converter output voltage. This information is used for the reg- ulation and the “output low” detection (VOUTL) that drastically speed−up the loop response when the output voltage drops below 95.5% of the wished level. 3 RT The resistor placed between pin 3 and ground adjusts the maximum on−time of our system for both phases, and hence the maximum power that can be delivered by the PFC stage. 4 OSC Connect a capacitor to set the clamp frequency of the PFC stage. If wished, this frequency can be reduced in light load as a function of the resistor placed between pin 6 and ground (frequency fold−back). If the coil current cycle is longer than the selected switching period, the circuit delays the next cycle until the core is reset. Hence, the PFC stage can operate in Critical Conduction Mode in the most stressful conditions. 5 VControl The error amplifier output is available on this pin. The capacitor connected between this pin and ground adjusts the regulation loop bandwidth that is typically set below 20 Hz to achieve high Power Factor ratios. Pin5 is grounded when the circuit is off so that when it starts operation, the power increases slowly (soft−start). 6 Freq. Foldback Apply a resistor between pin 6 and ground to adjust the oscillator charge current. Clamped not to exceed 100 mA, this charge current is made proportional to the power level for a reduced switching frequency at light load and an optimum efficiency over the load range. 7 BO (Brown−out Protection) Apply an averaged portion of the input voltage to detect brown−out conditions when Vpin2 drops below 1 V. A 50−ms internal delay blanks short mains interruptions to help meet hold−up time re- quirements. When it detects a brown−out condition, the circuit stops pulsing and grounds the “pfcOK” pin to disable the downstream converter. Also an internal 7−mA current source is activated to offer a programmable hysteresis. The pin2 voltage is internally re−used for feed−forward. Grounding pin 7 disables the part (after the 50−ms blanking time has elapsed). 8 OVP / UVP The circuit turns off when Vpin9 goes below 480 mV (UVP) and disables the drive as long as the pin voltage exceeds 2.5 V (OVP). 9 CS This pin monitors a negative voltage proportional to the coil current. This signal is sensed to limit the maximum coil current and protect the PFC stage in presence of in−rush currents. 10 Latch Apply a voltage higher than 2.5 V to latch−off the circuit. The device is reset by unplugging the PFC stage (practically when the circuit detects a brown−out detection) or by forcing the circuit VCC below VCCRST (4 V typically). Operation can then resume when the line is applied back. 11 DRV2 This is the gate drive pin for phase 2 of the interleaved PFC stage. The high current capability of the totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate charge power MOSFETs. 12 VCC This pin is the positive supply of the IC. The circuit starts to operate when VCC exceeds 12 V and turns off when VCC goes below 10 V (typical values). After start−up, the operating range is 9.5 V up to 20 V. 13 GND Connect this pin to the pre−converter ground. 14 DRV1 This is the gate drive pin for phase 1 of the interleaved PFC stage. The high current capability of the totem pole gate drive (+0.5/−0.8 A) makes it suitable to effectively drive high gate charge power MOSFETs. 15 REF5V / pfcOK The pin15 voltage is high (5 V) when the PFC stage is in a normal, steady state situation and low otherwise. This signal serves to “inform” the downstream converter that the PFC stage is ready and that hence, it can start operation. 16 ZCD1 This is the zero current detection pin for phase 1 of the interleaved PFC stage. Apply the voltage from an auxiliary winding to detect the core reset of the inductor and the valley of the MOSFET drain source voltage. |
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