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STM32F405RG Datasheet(PDF) 25 Page - STMicroelectronics

Part No. STM32F405RG
Description  ARM Cortex-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F405RG Datasheet(HTML) 25 Page - STMicroelectronics

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STM32F405xx, STM32F407xx
Description
Doc ID 022152 Rev 3
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Figure 7.
Regulator ON/internal reset OFF
Regulator OFF
This mode allows to power the device as soon as VDD reaches 1.8 V.
Regulator OFF/internal reset ON
This mode is available only on UFBGA and WLCSP90 packages. It is activated by
setting BYPASS_REG and PDR_ON pins to VDD.
The regulator OFF/internal reset ON mode allows to supply externally a 1.2 V voltage
source through VCAP_1 and VCAP_2 pins, in addition to VDD.
The following conditions must be respected:
–VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
If the time for VCAP_1 and VCAP_2 to reach 1.08 V is faster than the time for VDD to
reach 1.8 V, then PA0 should be connected to the NRST pin (see Figure 8).
Otherwise, PA0 should be asserted low externally during POR until VDD reaches
1.8 V (see Figure 9).
–If VCAP_1 and VCAP_2 go below 1.08 V and VDD is higher than 1.7 V, then a reset
must be asserted on PA0 pin.
In regulator OFF/internal reset ON mode, PA0 cannot be used as a GPIO pin since it
allows to reset the part of the 1.2 V logic which is not reset by the NRST pin, when the
internal voltage regulator in off.
Regulator OFF/internal reset OFF
This mode is available only on UFBGA and WLCSP packages. It is activated by setting
BYPASS_REG pin to VDD and by applying an inverted reset signal to PDR_ON, and


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