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STM32F405RG Datasheet(PDF) 77 Page - STMicroelectronics

Part No. STM32F405RG
Description  ARM Cortex-M4 32b MCUFPU, 210DMIPS, up to 1MB Flash/1924KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F405RG Datasheet(HTML) 77 Page - STMicroelectronics

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STM32F405xx, STM32F407xx
Electrical characteristics
Doc ID 022152 Rev 3
77/180
Typical and maximum current consumption
The MCU is placed under the following conditions:
At startup, all I/O pins are configured as analog inputs by firmware.
All peripherals are disabled except if it is explicitly mentioned.
The Flash memory access time is adjusted to fHCLK frequency (0 wait state from 0 to
30 MHz, 1 wait state from 30 to 60 MHz, 2 wait states from 60 to 90 MHz, 3 wait states
from 90 to 120 MHz, 4 wait states from 120 to 150 MHz, and 5 wait states from 150 to
168 MHz).
When the peripherals are enabled HCLK is the system clock, fPCLK1 = fHCLK/4, and
fPCLK2 = fHCLK/2, except is explicitly mentioned.
The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature
(TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified.
Table 19.
Typical and maximum current consumption in Run mode, code with data processing
running from Flash memory (ART accelerator disabled)
Symbol
Parameter
Conditions
fHCLK
Typ
Max(1)
Unit
TA = 25 °C TA = 85 °C TA = 105 °C
IDD
Supply current
in Run mode
External clock(2),
all peripherals
enabled(3)(4)
168 MHz
93
109
117
mA
144 MHz
76
89
96
120 MHz
67
79
86
90 MHz
53
65
73
60 MHz
37
49
56
30 MHz
20
32
39
25 MHz
16
27
35
16 MHz
11
23
30
8 MHz
6
18
25
4 MHz
4
16
23
2 MHz
3
15
22
External clock(2),
all peripherals
disabled(3)(4)
168 MHz
46
61
69
144 MHz
40
52
60
120 MHz
37
48
56
90 MHz
30
42
50
60 MHz
22
33
41
30 MHz
12
24
31
25 MHz
10
21
29
16 MHz
7
19
26
8 MHz
4
16
23
4 MHz
3
15
22
2 MHz
2
14
21
1.
Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2.
External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.


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