ISL37231

7

FN8266.1

January 25, 2013

Operation

The ISL37231 is a robust signal conditioner that ensures

maximum performance across a variety of time-varying and

unpredictable environments. Endowed with functions, such as

transmit and receive equalization, signal retiming, and

programmable impedance termination, this IC fortifies sensitive

links that break with other retiming-based solutions. To facilitate

systems analysis, the ISL37231 additionally provides visibility of

link conditions by way of loopback modes, PRBS generators with

error counters, and an on-chip eye-monitor.

Equalization

The ISL37231 equalizes each received signal with a highly

adjustable equalizer.

Each received signal is equalized with a five stage

continuous-time linear filter that can be optimized for either

copper cable skin loss or dielectric loss. The amount of

equalization is selectable between 0dB and 16.5dB of

compensation in increments of 1.5dB. Because the filter is

phase/jitter-optimized, the maximum 16.5dB compensation

level yields very low jitter for its targeted 2m (~20dB) 34AWG

cable length.

In addition to supporting a wide variety of programmable

settings, all channel equalizers can be trained upon power up to

minimize jitter. The training of all channels is completed within

2.5ms of receiving valid data on the input ports after power up.

Retiming

To provide maximum system robustness, the ISL37231 retimes

each of the four data paths in the device prior to output. With

independent PLLs for each channel, the device can operate each

channel with asynchronous baud rates thereby permitting a high

degree of system flexibility. Examples where such flexibility is

crucial include independent or staggered SSC rates across

different channels and asymmetric transmission where up and

down-stream channels operate at different baud rates.

Each retimer has high input jitter tolerance and can output less

than 0.3UI of total jitter (provided the inherent RJ of the test

equipment is de-embedded and no input low-frequency periodic

jitter is present).

Output De-Emphasis

The drive level output of any channel is adjustable from 200 to

950mVppd rail-to-rail (170 to 807.5mVppd eye height) in 16

equal increments.

Each driver supports output equalization with one tap of

pre-cursor and one tap of post-cursor de-emphasis. The gains on

the pre and post-cursor taps are adjustable between 0 and -1

relative to the main tap in increments of 1/128. The output

amplitude and de-emphasis for each channel can be

independently programmed to accommodate routing variation

between lanes.

Loopback

To facilitate system diagnostics, a loopback mode is available for

each signal direction. In particular, for each lane, two loopback

paths are provided:

• Near-End/PCB Loopback: The received on-ramp signal is

directed back into the off-ramp output driver. This includes

PCB equalization, limiting, retiming, and PCB de-emphasis.

• Far-End/Cable Loopback: The received off-ramp signal is

directed back into the on-ramp output driver. This includes

cable equalization, limiting, retiming, and cable de-emphasis.

Eye Monitor

For accurate and detailed analysis of signal integrity, each

channel in the ISL37231 can provide an on-chip eye-diagram of

its respective equalizing filter output. This eye diagram can be

used to evaluate jitter and eye height at the input of the retime

circuit’s slicer.

The eye monitor (in conjunction with the on-chip microcontroller)

generates up to a 50 pixel x 50 pixel resolution eye-diagram (i.e.

down to 0.02 UI resolution in the time domain and 12mV

resolution in the voltage domain) that can be read over the UART

interface. The output eye diagram represents an estimated

probability density function for the equalized signal under

investigation.

Besides providing a full eye-diagram, the Eye-Monitor can also be

directed to output only the temporal and/or voltage eye-opening

for a more concise signal fidelity assessment (i.e., jitter and eye

height, respectively).

Polarity Inversion

To accommodate uncertainty in signal polarity (as may be

associated with differential cable receive pairs), each channel

can be independently programmed to invert its polarity.

On-Chip Microcontroller

An internal microcontroller is used to manage the operation of

the ISL37231.

The microcontroller communicates with the system host over a

UART interface. Because the ISL37231 UART interface operates

at 1.8V, an interfacing IC (such as the ISL80083) is required for

applications needing 3.3V levels and tri-state (push/pull/no-load)

operation.

• Instruct a power-regulator providing the 1.0V supply that the

system is entering sleep mode and power can be removed

from non-critical 1.0V rails for maximum power savings during

sleep state.

• Load firmware from an external EEPROM.