Electronic Components Datasheet Search |
|
AD9857AST Datasheet(PDF) 3 Page - Analog Devices |
|
AD9857AST Datasheet(HTML) 3 Page - Analog Devices |
3 / 31 page –3– AD9857 REV. 0 Test AD9857 Parameter Temp Level Min Typ Max Unit SPURIOUS POWER (Off Channel, Measured in Equivalent Bandwidth), Output Attenuated 18 dB Relative to Full Scale 6.4 MHz Bandwidth 25 °C IV –51 dBc 3.2 MHz Bandwidth 25 °C IV –54 dBc 1.6 MHz Bandwidth 25 °C IV –56 dBc 0.8 MHz Bandwidth 25 °C IV –59 dBc 0.4 MHz Bandwidth 25 °C IV –62 dBc 0.2 MHz Bandwidth 25 °C IV –63 dBc TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency 25 °C I 10 MHz Minimum Clock Pulsewidth Low (tPWL)25 °CI 30 ns Minimum Clock Pulsewidth High (tPWH)25 °CI 30 ns Maximum Clock Rise/Fall Time 25 °CI 1 ms Minimum Data Setup Time (tDS)25 °CI 30 ns Minimum Data Hold Time (tDH)25 °CI 0 ns Maximum Data Valid Time (tDV)25 °CI 35 ns Wake-Up Time 1 25 °CI 1 ms Minimum RESET Pulsewidth High (tRH)25 °C I 5 SYSCLK2 Cycles Minimum CS Setup Time 25 °CI 40 ns CMOS LOGIC INPUTS Logic “1” Voltage 25 °C I 2.0 V Logic “0” Voltage 25 °C I 0.8 V Logic “1” Current 25 °CI 5 µA Logic “0” Current 25 °CI 5 µA Input Capacitance 25 °CV 3 pF CMOS LOGIC OUTPUTS (1 mA LOAD) Logic “1” Voltage 25 °C I 2.7 mA Logic “0” Voltage 25 °C I 0.4 mA POWER SUPPLY VS CURRENT 3 (All Power Specs at VDD = 3.3 V, 25 °C, REFCLK = 200 MHz) Full Operating Conditions 25 °C I 615 mA 160 MHz Clock ( ×16) 25 °C I 515 mA 120 MHz Clock ( ×12) 25 °C I 400 mA Burst Operation (25%) 25 °C I 450 mA Single-Tone Mode 25 °C I 310 mA Power-Down Mode 25 °CI 80 mA Full-Sleep Mode 25 °C I 13.5 mA NOTES 1Wake-Up Time refers to recovery from Full Sleep Mode. The longest time required is for the Reference Clock Multiplier PLL to lock up (if it is being used). The Wake-Up Time assumes that there is no capacitor on DAC_BP, and that the recommended PLL loop filter values are used. The state of the Reference Clock Multi- plier lock can be determined by observing the signal on the PLL_LOCK pin. 2SYSCLK refers to the actual clock frequency used on-chip by the AD9857. If the Reference Clock Multiplier is used to multiply the external reference frequency, the SYSCLK frequency is the external frequency multiplied by the Reference Clock Multiplier multiplication factor. If the Reference Clock Multiplier is not used, the SYSCLK frequency is the same as the external REFCLK frequency. 3CIC = 2, INV SINC ON, FTW = 40%, PLL OFF, Auto Power-Down Between Burst On, TxENABLE Duty Cycle = 25%. Specifications subject to change without notice. |
Similar Part No. - AD9857AST |
|
Similar Description - AD9857AST |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |