AD9832 datasheet(3/16 Pages) AD

Part #	AD9832

Description	CMOS Complete DDS

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Manufacturer	AD [Analog Devices]

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–3–

AD9832

REV. A

TIMING CHARACTERISTICS (V

DD = +3.3 V

10%; +5 V

10%; AGND = DGND = 0 V, unless otherwise noted)

Limit at

TMIN to TMAX

Parameter

(B Version)

Units

Test Conditions/Comments

t1

40

ns min

MCLK Period

t2

16

ns min

MCLK High Duration

t3

16

ns min

MCLK Low Duration

t4

50

ns min

SCLK Period

t5

20

ns min

SCLK High Duration

t6

20

ns min

SCLK Low Duration

t7

15

ns min

FSYNC to SCLK Falling Edge Setup Time

t8

20

ns min

FSYNC to SCLK Hold Time

SCLK – 5

ns max

t9

15

ns min

Data Setup Time

t10

5

ns min

Data Hold Time

t11

8

ns min

FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge

t11A*

8

ns min

FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge

*See Pin Function Descriptions.

Guaranteed by design but not production tested.

MCLK

t2

t1

t3

Figure 2. Master Clock

SCLK

FSYNC

SDATA

t5

t4

t6

t7

t8

t10

t9

D15

D14

D2

D1

D0

D15

D14

Figure 3. Serial Timing

t11A

t11

VALID DATA

MCLK

FSELECT

PSEL0, PSEL1

Figure 4. Control Timing

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