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AD9768 Datasheet(PDF) 2 Page - Analog Devices |
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AD9768 Datasheet(HTML) 2 Page - Analog Devices |
2 / 4 page REV. A –2– AD9768–SPECIFICATIONS (typical @ +25 C under following conditions unless otherwise noted; nominal digital input levels; nominal power supplies; RL = 50 ; RSET = 220 ; VRET = 0 V) AD9768SD D/A Schematic Parameter Unit AD9768SJD/SD/SE RESOLUTION(FS = FULL SCALE) Bits 8 LSB WEIGHT (CURRENT) µA78 ACCURACY 1 Differential Nonlinearity ± % FS 0.2 Integral Nonlinearity ± % FS 0.2 Monotonicity Guaranteed Zero Offset (lnitial) µA60 TEMPERATURE COEFFICIENTS Zero Offset ppm/ °C 1.5 Reference Voltage (–1.26 V) ppm/ °C70 DIGITAL DATA INPUTS Logic Compatibility ECL Logic Voltage Levels “l” = V –0.9 “0” = V –1.7 Coding Binary (BIN) = Unipolar Out Offset Binary (OBN) = Bipolar Out OUTPUT Current (Unipolar) FS mA (max) 2 to 20 (30) IOUT (@ Pin 13) All Digital “1” Input mA 20 All Digital “0” Input mA 0 IOUT(@ Pin 14) All Digital “l” Input mA 0 All Digital “0” Input mA 20 Compliance V (Pin 13) –0.7 to +3.0 V (Pin 14) –1.1 to +3.0 Impedance Ω (±15%) 750 SPEED PERFORMANCE Settling Time (to 0.2% FS) 2 ns 5 Slew Rate V/ µs 400 Update Rate MSPS 100 Rise Time ns 1.8 Glitch Energy pV-sec 200 REFERENCE Internal, Monolithic 3 V –1.26 External, Variable 4 Voltage-Multiplying Mode V (max) 0 to –1.1 (–2) Current-Multiplying Mode mA (max) 0 to –5 (–7.5 ) VOLTAGE-MULTIPLYING MODE 4 (See Figure 2) VM Range (at Pin 16) V ±0.5 VM Center V –0.6 Resistance (at Pin 16) k Ω 800 Transfer Function – Measured at Pin 13; Digital “0” Applied to Bits 1-8: –0.1 VM Input = 0 mA IOUT –1.1 VM Input = 0 mA IOUT Measured at Pin 13; Digital “1” Applied to Bits 1-8: –0.1 VM Input = 1 mA IOUT –1.1 VM Input = 20 mA IOUT Large Signal Bandwidth (–3 dB Point) kHz 250 Parameter Unit AD9768SJD/SD/SE CURRENT-MULTIPLYING MODE (See Figure 4) IM Range (at Pins 17 & 18) mA 0 to 5 Resistance (at Pin 18) Ω 160 Transfer Function – Measured at Pin 13; Digital “0” Applied to Bits 1-8: 1 mA IM Input = 0 mA IOUT 5 mA IM Input = 0 mA IOUT Measured at Pin 13; Digital “1” Applied to Bits 1-8: 1 mA IM Input = 4 mA IOUT 5 mA IM Input = 20 mA IOUT Large Signal Bandwidth (–3dB Point) MHz 40 POWER REQUIREMENTS –5.2 V ±0.25 mA (max) 66(70) +5.0 V ±0.25 mA (max) 14(15) Power Dissipation mW (max) 410(430) Power Supply Sensitivity 5 %/% 0.07 TEMPERATURE RANGES 6 Operating AD9768JD °C 0 to +70 AD9768SD/SE °C –55 to +125 Storage °C –55 to +150 THERMAL RESlSTANCE 7 Junction to Air, θ JA (Free Air) °C/W 90 Junction to Case, θ JA °C/W 20 PACKAGE OPTION 8 Ceramic (D-18) AD9768JD AD9768SD LCC (E-20A) AD9768SE NOTES 1Relative to FS, including linearity (within voltage compliance limits). 2Worst case settling time; includes FS and Most Significant Bit (MSB) transitions. 3Applies when operating AD9768 as standard D/A. 4Based on R L = 50 ohms; RSET = 220 ohms; VRET = 0 V. 51% change in either power supply voltage causes 0.07% change in analog output. 6Case temperature. 7Maximum junction temperature 125 °C. 8D = Ceramic DIP, E = Leadless Ceramic Chip Carrier. Specifications subject to change without notice. |
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