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MMA8491Q Datasheet(PDF) 14 Page - Freescale Semiconductor, Inc
FREESCALE [Freescale Semiconductor, Inc]
MMA8491Q Datasheet(HTML) 14 Page - Freescale Semiconductor, Inc
/ 26 page
Freescale Semiconductor, Inc.
Serial Interface (I
Acceleration data may be accessed through an I
C interface thus making the device particularly suitable for direct interfacing with
a microcontroller. The MMA8491Q features three interrupt signals which indicate the tilt-sensing results on X, Y, Z axis
respectively. The raw accelerometer data are readable via I
C at the same time when interrupt signal is available.
The registers embedded inside the MMA8491Q are accessible through the I
C serial interface (Table 8). To enable the I
interface, the EN pin must be HIGH. If either EN or V
are absent, the MMA8491Q I
C interface reads invalid data. The I
interface may be used for communications along with other I
C devices. Removing power from the V
pin of the MMA8491Q
does not affect the I
There are two signals associated with the I
C bus; the Serial Clock Line (SCL) and the Serial Data Line (SDA). The latter is a
bidirectional line used for sending and receiving the data to/from the interface. External pullup resistors connected to V
expected for SDA and SCL. When the bus is free both the lines are HIGH. The I
C interface is compliant with Fast mode (400 kHz,
The transaction on the bus is started through a start condition (START) signal. A START condition is defined as a HIGH-to-LOW
transition on the data line while the SCL line is held HIGH.
After START has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after START
contains the slave address in the first 7 bits, and the 8th bit tells whether the Master is receiving data from the slave or transmitting
data to the slave. When an address is sent, each device in the system compares the first 7 bits after a start condition with its
address. If they match, then the device considers itself addressed by the Master.
The 9th clock pulse, following the slave address byte (and each subsequent byte), is the acknowledge (ACK). The transmitter
must release the SDA line during the ACK period. The receiver must then pull the data line LOW so that it remains stable low
during the high period of the acknowledge clock period.
A LOW-to-HIGH transition on SDA while SCL is HIGH is defined as a stop condition (STOP). A data transfer is always terminated
by a STOP.
A Master may also issue a repeated START during a data transfer. The MMA8491Q expects repeated STARTs to be used to
randomly read from specific registers.
The MMA8491Q accelerometer standard 7-bit slave address is 01010101(0x55).
Single byte read
The transmission of an 8-bit command begins on the falling edge of SCL. After the 8 clock cycles are used to send the command,
note that the data returned is sent with the MSB first after the data is received. Figure 10 shows the timing diagram for the
accelerometer 8-bit I
C read operation.
The Master (or MCU) transmits a start condition (ST) to the MMA8491Q, slave address (0x55), with the R/W bit set to
“0” for a write, and the MMA8491Q sends an acknowledgement.
Then the Master (or MCU) transmits the address of the register to read and the MMA8491Q sends an
The Master (or MCU) transmits a repeated start condition (SR) and then addresses the MMA8491Q (0x1D) with the R/
W bit set to “1” for a read from the previously selected register.
The Slave then acknowledges and transmits the data from the requested register.
The Master does not acknowledge (NAK) the transmitted data, but transmits a stop condition to end the data transfer.
Table 8. Serial interface pins
C Serial Clock
C Serial Data
Table 9. I
C device address sequence
8-bit Final Value
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