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MMA8491Q Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc

Part No. MMA8491Q
Description  Xtrinsic MMA8491Q 3-Axis Multifunction Digital Accelerometer
Download  26 Pages
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Maker  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
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MMA8491Q Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc

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MMA8491Q
Sensors
10
Freescale Semiconductor, Inc.
2.4
I2C interface characteristics
Figure 6. I2C slave timing diagram
Table 6. I2C slave timing values(1)
1.All values referred to VIH(min) (0.3VDD) and VIL(max) (0.7VDD) levels.
Parameter
Symbol
I2C Fast Mode
Unit
Min
Max
SCL clock frequency
fSCL
0
400
kHz
Bus-free time between STOP and START condition
tBUF
1.3
μs
(Repeated) START hold time
tHD;STA
0.6
μs
Repeated START setup time
tSU;STA
0.6
μs
STOP condition setup time
tSU;STO
0.6
μs
SDA data hold time
tHD;DAT
0.05
0.9 (2)
2.This device does not stretch the LOW period (tLOW) of the SCL signal.
μs
SDA setup time
tSU;DAT
100
ns
SCL clock low time
tLOW
1.3
μs
SCL clock high time
tHIGH
0.6
μs
SDA and SCL rise time
tr
20 + 0.1 Cb
(3)
3.Cb = total capacitance of one bus line in pF.
300
ns
SDA and SCL fall time
tf
20 + 0.1 Cb
(3)
300
ns
SDA valid time (4)
4.tVD;DAT = time for data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
tVD;DAT
0.9 (2)
μs
SDA valid acknowledge time (5)
5.tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).
tVD;ACK
0.9 (2)
μs
Pulse width of spikes on SDA and SCL that must be suppressed by
internal input filter
tSP
050
ns
Capacitive load for each bus line
Cb
400
pF
VIL = 0.3VDD
VIH = 0.7VDD


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