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AD8348XXX Datasheet(PDF) 6 Page - Analog Devices |
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AD8348XXX Datasheet(HTML) 6 Page - Analog Devices |
6 / 13 page PRELIMINARY TECHNICAL DATA Rev. PrF 2/11/03 - 6 - PIN FUNCTION DESCRIPTIONS Pin Name Description Equiv. Cir. 1,28 LOIP,LOIN LO Input. For optimum performance, these inputs should be driven differentially. Typical input drive level is equal to –10 dBm. To obtain a broadband 50 Ω input impedance, connect a 60.4 Ω shunt resistor between LOIP and LOIN. 2, 12, 20 VPS1, VPS2, VPS3 Positive Supply for LO, IF, and Biasing & Baseband sections respectively. Each of these pins should be decoupled with 0.1 uF and 100 pF capacitors. 3,4, 25, 26 IOPN,IOPP, QOPP, QOPN I- and Q-channel differential baseband outputs. Typical output swing is equal to 2Vpp differential. The DC common-mode voltage level on these pins is set by the voltage on VCMO. 5 VCMO Baseband DC common-mode voltage. The voltage applied to this pin sets the DC common-mode levels for all the baseband outputs and inputs (IMXO, QMXO, IOPP, IOPN, QOPP, QOPN, IAIN and QAIN). This pin can either be connected to VREF or to a reference voltage from another device, such as an ADC). 6 IAIN I-channel baseband amplifier input. The single-ended signal on this pin is referenced to VCMO and should have a DC bias equal to the DC voltage on the VCMO pin. If IAIN is DC-coupled to IMXO, biasing will be provided by IMXO. If an AC-coupled filter is placed between IMXO and IAIN, this pin can be biased from VREF through a 1 k Ω resistor. The gain from IAIN to the differential outputs IOPN/IOPP is 20 dB. 7,22 COM3 Ground for Biasing and Baseband sections. 8,21 IMXO, QMXO I- and Q-channel mixer baseband outputs. These are low impedance (40 Ohms) outputs whose bias level is set by the voltage on the VCMO pin. These pins are typically connected to IAIN and QAIN respectively, either directly or through a filter. These outputs can drive a maximum current of 2.5 mA 9 COM2 IF Section Ground 10, 11 IFIN,IFIP IF Input. IFIN should be AC-coupled to ground. The single-ended IF input signal should be AC-coupled into IFIP. The nominal differential impedance of these pins is 200 Ohms. For a broadband 50 Ω input impedance, a minimum loss L-pad should be used. Rseries=174 Ohms, Rshunt=57.6 Ohms. 13, 16 IOFS, QOFS I- and Q-channel offset nulling inputs. DC offsets on the I-channel mixer output (IMXO) can be nulled by connecting a 0.1 uF capacitor from IOFS to ground. Driving IOFS with a fixed voltage (typically from a DAC) can extended the operating frequency range to include DC by nulling out the offset at the baseband outputs. 14 VREF Reference Voltage Output. This output voltage (1V) is the main bias level for the device and can be used to externally bias the inputs and outputs of the baseband amplifiers. 15 ENBL Chip Enable Input. Active high. Threshold is equal to +Vs/2. 17 VGIN Gain Control Input. The voltage on this pin controls the gain on the RF VGA. The gain control voltage range is from 0.2 V to 1.2 V and corresponds to a conversion gain range from +25 dB to –18 dB. This is the gain to the output of the mixers (i.e. QMXO and IMXO). There is an additional 20 dB of gain in the final baseband amplifiers (IAIN to IOPP/IOPN and QAIN to QOPP/QOPN). Note that the gain control function has a negative sense (i.e. increasing voltage decreases gain). 18, 19 MXIP, MXIN Auxiliary mixer inputs. If ENVG is low then the IFIP, IFIN inputs are disabled and MXIP, MXIN are enabled, allowing the VGA to be bypassed. This is a fully differential input which should be AC coupled to the signal source. 23 QAIN Q-channel baseband amplifier input. The single-ended signal on this pin is referenced to VCMO and should have a DC bias equal to the DC voltage on the VCMO pin. If QAIN is DC-coupled to QMXO, biasing will be provided by QMXO. If an AC-coupled filter is placed between QMXO and QAIN, this pin can be biased from VREF through a 1 k Ω resistor. The gain from QAIN to the differential outputs QOPN/QOPP is 20 dB. 24 ENVG Active high VGA enable. When ENVG is high, IFIP, IFIN inputs are enabled and MXIP, MXIN inputs are disabled. When ENVG is low, MXIP, MXIN inputs are enabled and IFIP, IFIN inputs are disabled. 27 COM1 LO Section Ground AD8348 |
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