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AD8323 Datasheet(PDF) 3 Page - Analog Devices

Part No. AD8323
Description  5 V CATV Line Driver Fine Step Output Power Control
Download  16 Pages
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD8323 Datasheet(HTML) 3 Page - Analog Devices

 
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AD8323
–3–
LOGIC INPUTS (TTL/CMOS Compatible Logic)
Parameter
Min
Typ
Max
Unit
Logic “1” Voltage
2.1
5.0
V
Logic “0” Voltage
0
0.8
V
Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN
020
nA
Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN
–600
–100
nA
Logic “1” Current (VINH = 5 V) PD
50
190
µA
Logic “0” Current (VINL = 0 V) PD
–250
–30
µA
Logic “1” Current (VINH = 5 V) SLEEP
50
190
µA
Logic “0” Current (VINL = 0 V) SLEEP
–250
–30
µA
TIMING REQUIREMENTS
Parameter
Min
Typ
Max
Unit
Clock Pulsewidth (TWH)
16.0
ns
Clock Period (TC)
32.0
ns
Setup Time SDATA vs. Clock (TDS)
5.0
ns
Setup Time
DATEN vs. Clock (T
ES)
15.0
ns
Hold Time SDATA vs. Clock (TDH)
5.0
ns
Hold Time
DATEN vs. Clock (T
EH)
3.0
ns
Input Rise and Fall Times, SDATA,
DATEN, Clock (T
R, TF)10
ns
TES
VALID DATA WORD G1
MSB. . . .LSB
GAIN TRANSFER (G1)
TDS
TEH
8 CLOCK CYCLES
GAIN TRANSFER (G2)
TOFF
TGS
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
PD
PEDESTAL
CLK
SDATA
DATEN
TON
TC
TWH
VALID DATA WORD G2
Figure 2. Serial Interface Timing
VALID DATA BIT
MSB
MSB-1
MSB-2
TDS
TDH
SDATA
CLK
Figure 3. SDATA Timing
(Full Temperature Range, VCC = 5 V, TR = TF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
(
DATEN, CLK, SDATA, PD, SLEEP, V
CC = 5 V: Full Temperature Range)


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