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AD808-622BRRL Datasheet(PDF) 5 Page - Analog Devices |
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AD808-622BRRL Datasheet(HTML) 5 Page - Analog Devices |
5 / 12 page AD808 REV. 0 –5– Damping Factor, ζ Damping factor, ζ describes the compensation of the second order PLL. A larger value of ζ corresponds to more damping and less peaking in the jitter transfer function. Acquisition Time This is the transient time, measured in bit periods, required for the AD808 to lock onto input data from its free-running state. Symmetry—Recovered Clock Duty Cycle Symmetry is calculated as (100 × on time)/period, where on time equals the time that the clock signal is greater than the midpoint between its “0” level and its “1” level. BINARY OUTPUT SCOPE PROBE AD808 QUANTIZER VCM VCM 4mVp-p INPUT a. Single-Ended Input Application BINARY OUTPUT SCOPE PROBE AD808 QUANTIZER VCM VCM 2mVp-p +INPUT –INPUT b. Differential Input Application Figure 3. (a–b) Single-Ended and Differential Input Applications 500 500 5k 5k AVEE AVCC OUT PIN NIN a. Quantizer Differential Input Stage 6k THRADJ AVEE 80k 1.2V +VBE b. Threshold Adjust 30 VCC1 SDOUT VEE IOL IOH 30 c. Signal Detect Output (SDOUT) 140 140 VCC2 DIFFERENTIAL OUTPUT VEE 7.8mA d. PLL Differential Output Stage—DATAOUT(N), CLKOUT(N) Figure 4. (a–d) Simplified Schematics The AD808 has internal circuits to set the common-mode volt- age at the quantizer inputs PIN (Pin 13) and NIN (Pin 12) as shown in Figure 4a. This allows very simple capacitive coupling of the signal from the preamp in the AD808 as shown in Figure 3. The internal common-mode potential is a diode drop (ap- proximately 0.8 V) below the positive supply as shown in Figure 4a. Since the common mode is referred to the positive supply, it is useful to bypass the common mode of the preamp to the positive supply as well, if this is an option. Note, it is not neces- sary to use capacitive coupling of the input signal with the AD808. Figure 14 shows the input common-mode voltage can be externally set. |
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