Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

AD808-622BRRL Datasheet(PDF) 5 Page - Analog Devices

Part # AD808-622BRRL
Description  Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
Download  12 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD808-622BRRL Datasheet(HTML) 5 Page - Analog Devices

  AD808-622BRRL Datasheet HTML 1Page - Analog Devices AD808-622BRRL Datasheet HTML 2Page - Analog Devices AD808-622BRRL Datasheet HTML 3Page - Analog Devices AD808-622BRRL Datasheet HTML 4Page - Analog Devices AD808-622BRRL Datasheet HTML 5Page - Analog Devices AD808-622BRRL Datasheet HTML 6Page - Analog Devices AD808-622BRRL Datasheet HTML 7Page - Analog Devices AD808-622BRRL Datasheet HTML 8Page - Analog Devices AD808-622BRRL Datasheet HTML 9Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 12 page
background image
AD808
REV. 0
–5–
Damping Factor,
ζ
Damping factor,
ζ describes the compensation of the second
order PLL. A larger value of
ζ corresponds to more damping
and less peaking in the jitter transfer function.
Acquisition Time
This is the transient time, measured in bit periods, required for
the AD808 to lock onto input data from its free-running state.
Symmetry—Recovered Clock Duty Cycle
Symmetry is calculated as (100
× on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
BINARY
OUTPUT
SCOPE
PROBE
AD808 QUANTIZER
VCM
VCM
4mVp-p
INPUT
a. Single-Ended Input Application
BINARY
OUTPUT
SCOPE
PROBE
AD808 QUANTIZER
VCM
VCM
2mVp-p
+INPUT
–INPUT
b. Differential Input Application
Figure 3. (a–b) Single-Ended and Differential Input
Applications
500
500
5k
5k
AVEE
AVCC
OUT
PIN
NIN
a. Quantizer Differential Input Stage
6k
THRADJ
AVEE
80k
1.2V +VBE
b. Threshold Adjust
30
VCC1
SDOUT
VEE
IOL
IOH
30
c. Signal Detect Output (SDOUT)
140
140
VCC2
DIFFERENTIAL
OUTPUT
VEE
7.8mA
d. PLL Differential Output Stage—DATAOUT(N),
CLKOUT(N)
Figure 4. (a–d) Simplified Schematics
The AD808 has internal circuits to set the common-mode volt-
age at the quantizer inputs PIN (Pin 13) and NIN (Pin 12) as
shown in Figure 4a. This allows very simple capacitive coupling
of the signal from the preamp in the AD808 as shown in Figure
3. The internal common-mode potential is a diode drop (ap-
proximately 0.8 V) below the positive supply as shown in Figure
4a. Since the common mode is referred to the positive supply, it
is useful to bypass the common mode of the preamp to the
positive supply as well, if this is an option. Note, it is not neces-
sary to use capacitive coupling of the input signal with the
AD808. Figure 14 shows the input common-mode voltage can
be externally set.


Similar Part No. - AD808-622BRRL

ManufacturerPart #DatasheetDescription
logo
Analog Devices
AD808 AD-AD808_15 Datasheet
153Kb / 12P
   Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
REV. 0
More results

Similar Description - AD808-622BRRL

ManufacturerPart #DatasheetDescription
logo
Analog Devices
AD807 AD-AD807_00 Datasheet
472Kb / 12P
   Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
REV. B
AD807 AD-AD807_15 Datasheet
472Kb / 12P
   Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
REV. B
AD807 AD-AD807 Datasheet
226Kb / 12P
   Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
REV. A
AD808 AD-AD808_15 Datasheet
153Kb / 12P
   Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
REV. 0
logo
Agere Systems
1345 AGERE-1345 Datasheet
98Kb / 12P
   1345-Type Receiver with Clock Recovery and Data Retiming
logo
Micro Linear Corporatio...
ML4622 MICRO-LINEAR-ML4622 Datasheet
170Kb / 8P
   Fiber Optic Data Quantizer
logo
Analog Devices
AD800 AD-AD800_15 Datasheet
141Kb / 12P
   Clock Recovery and Data Retiming Phase-Locked Loop
REV. B
AD802 AD-AD802_15 Datasheet
141Kb / 12P
   Clock Recovery and Data Retiming Phase-Locked Loop
REV. B
AD800 AD-AD800 Datasheet
253Kb / 12P
   Clock Recovery and Data Retiming Phase-Locked Loop
REV. B
logo
Infineon Technologies A...
FOA3251B1 INFINEON-FOA3251B1 Datasheet
600Kb / 25P
   High Speed Clock and Data Recovery for Fiber Optic Applications
V1.0, Aug. 1999
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com