AD807

REV. A

–5–

Damping Factor,

ζ

Damping factor,

ζ describes the compensation of the second or-

der PLL. A larger value of

ζ corresponds to more damping and

less peaking in the jitter transfer function.

Acquisition Time

This is the transient time, measured in bit periods, required for

the AD807 to lock onto input data from its free-running state.

Symmetry—Recovered Clock Duty Cycle

Symmetry is calculated as (100

× on time)/period, where on

time equals the time that the clock signal is greater than the

midpoint between its “0” level and its “1” level.

Bit Error Rate vs. Signal-to-Noise Ratio

AD807 Bit Error Rate vs. Signal-to-Noise Ratio performance is

shown in Figure 11. Wideband amplitude noise is summed with

the input data signal as shown in Figure 4. Performance is

shown for input data levels of 5 mV and 10 mV.

BINARY

OUTPUT

EPITAXX ERM504

SCOPE

2mVp-p

a. Single-Ended Input Application

BINARY

OUTPUT

AD8015

DIFFERENTIAL

OUTPUT TIA

SCOPE

1mVp-p

+OUT

–OUT

b. Differential Input Application

Figure 3. (a–b) Single-Ended and Differential Input

Applications

DIFFERENTIAL

SIGNAL

SOURCE

∑

∑

POWER

SPLITTER

NOISE

SOURCE

FILTER

100MHz

D.U.T.

AD807

POWER COMBINER

POWER

COMBINER

50

Ω

0.47µF

75

Ω

100

Ω

1.0µF

GND

+5V

PIN

NIN

+

+

+

–

50

Ω

0.47µF

Figure 4. Bit Error Rate vs. Signal-to-Noise Ratio

Test: Block Diagram

400

Ω

400

Ω

DIFFERENTIAL

INPUT

CURRENT SOURCES

HEADROOM

≥ 0.7V

0.8V

0.5mA

1mA

0.5mA

a. Quantizer Differential Input Stage

5.9k

Ω

THRADJ

94.6k

Ω

b. Threshold Adjust

150

Ω

SDOUT

150

Ω

c. Signal Detect Output (SDOUT)

450

Ω

450

Ω

DIFFERENTIAL

OUTPUT

2.5mA

d. PLL Differential Output Stage—DATAOUT(N),

CLKOUT(N)

Figure 5. (a–d) Simplified Schematics