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AD807 Datasheet(PDF) 4 Page  Analog Devices 

AD807 Datasheet(HTML) 4 Page  Analog Devices 
4 / 12 page REV. A –4– AD807 DEFINITION OF TERMS Maximum, Minimum and Typical Specifications Specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. Typical specifications are the mean of the distribution of the data for that parameter. If a parameter has a maximum (or a minimum), that value is calculated by adding to (or subtracting from) the mean six times the standard deviation of the distribu tion. This procedure is intended to tolerate production varia tions: if the mean shifts by 1.5 standard deviations, the remaining 4.5 standard deviations still provide a failure rate of only 3.4 parts per million. For all tested parameters, the test limits are guard banded to account for tester variation to thus guarantee that no device is shipped outside of data sheet specifications. Input Sensitivity and Input Overdrive Sensitivity and Overdrive specifications for the Quantizer in volve offset voltage, gain and noise. The relationship between the logic output of the quantizer and the analog voltage input is shown in Figure 1. For sufficiently large positive input voltage the output is always Logic 1 and similarly, for negative inputs, the output is always Logic 0. However, the transitions between output Logic Levels 1 and 0 are not at precisely defined input voltage levels, but oc cur over a range of input voltages. Within this Zone of Confu sion, the output may be either 1 or 0, or it may even fail to attain a valid logic state. The width of this zone is determined by the input voltage noise of the quantizer (650 µV at the 1 × 10–10 confidence level). The center of the Zone of Confusion is the quantizer input offset voltage ( ±500 µV maximum). Input Over drive is the magnitude of signal required to guarantee correct logic level with 1 × 10–10 confidence level. With a singleended PINTIA (Figure 3), ac coupling is used and the inputs to the Quantizer are dc biased at some common mode potential. Observing the Quantizer input with an oscillo scope probe at the point indicated shows a binary signal with average value equal to the commonmode potential and instan taneous values both above and below the average value. It is convenient to measure the peaktopeak amplitude of this signal and call the minimum required value the Quantizer Sensitivity. Referring to Figure 1, since both positive and negative offsets need to be accommodated, the Sensitivity is twice the Over drive. The AD807 Quantizer has 2 mV Sensitivity. With a differential TIA (Figure 3), Sensitivity seems to improve from observing the Quantizer input with an oscilloscope probe. This is an illusion caused by the use of a singleended probe. A 1 mV peaktopeak signal appears to drive the AD807 Quan tizer. However, the singleended probe measures only half the signal. The true Quantizer input signal is twice this value since the other Quantizer input is a complementary signal to the sig nal being observed. Response Time Response time is the delay between removal of the input signal and indication of Loss of Signal (LOS) at SDOUT. The re sponse time of the AD807 (1.5 µs maximum) is much faster than the SONET/SDH requirement (3 µs ≤ response time ≤ 100 µs). In practice, the time constant of the ac coupling at the Quantizer input determines the LOS response time. Nominal Center Frequency This is the frequency at which the VCO will oscillate with the loop damping capacitor, CD, shorted. Tracking Range This is the range of input data rates over which the AD807 will remain in lock. Capture Range This is the range of input data rates over which the AD807 will acquire lock. Static Phase Error This is the steadystate phase difference, in degrees, between the recovered clock sampling edge and the optimum sampling in stant, which is assumed to be halfway between the rising and falling edges of a data bit. Gate delays between the signals that define static phase error, and IC input and output signals pro hibit direct measurement of static phase error. Data Transition Density, ρ This is a measure of the number of data transitions, from “0” to “1” and from “1” to “0,” over many clock periods. ρ is the ratio (0 ≤ ρ ≤ 1) of data transitions to bit periods. Jitter This is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms or Unit Intervals (UI). Jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. Jitter on the recovered clock causes jitter on the retimed data. Output Jitter This is the jitter on the retimed data, in degrees rms, due to a specific pattern or some pseudorandom input data sequence (PRN Sequence). Jitter Tolerance Jitter Tolerance is a measure of the AD807’s ability to track a jittery input data signal. Jitter on the input data is best thought of as phase modulation, and is usually specified in unit intervals. The PLL must provide a clock signal that tracks the phase modulation in order to accurately retime jittered data. In order for the VCO output to have a phase modulation that tracks the input jitter, some modulation signal must be generated at the output of the phase detector. The modulation output from the phase detector can only be produced by a phase error between its data input and its clock input. Hence, the PLL can never perfectly track jittered data. However, the magnitude of the phase error depends on the gain around the loop. At low fre quencies, the integrator of the AD807 PLL provides very high gain, and thus very large jitter can be tracked with small phase errors between input data and recovered clock. At frequencies closer to the loop bandwidth, the gain of the integrator is much smaller, and thus less input jitter can be tolerated. The AD807 output will have a bit error rate less than 1 × 10–10 when in lock and retiming input data that has the CCITT G.958 specified jitter applied to it. Jitter Transfer (Refer to Figure 20) The AD807 exhibits a lowpass filter response to jitter applied to its input data. Bandwidth This describes the frequency at which the AD807 attenuates sinusoidal input jitter by 3 dB. Peaking This describes the maximum jitter gain of the AD807 in dB. 
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