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AD807 Datasheet(PDF) 5 Page - Analog Devices

Part No. AD807
Description  Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD807 Datasheet(HTML) 5 Page - Analog Devices

 
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AD807
REV. A
–5–
Damping Factor,
ζ
Damping factor,
ζ describes the compensation of the second or-
der PLL. A larger value of
ζ corresponds to more damping and
less peaking in the jitter transfer function.
Acquisition Time
This is the transient time, measured in bit periods, required for
the AD807 to lock onto input data from its free-running state.
Symmetry—Recovered Clock Duty Cycle
Symmetry is calculated as (100
× on time)/period, where on
time equals the time that the clock signal is greater than the
midpoint between its “0” level and its “1” level.
Bit Error Rate vs. Signal-to-Noise Ratio
AD807 Bit Error Rate vs. Signal-to-Noise Ratio performance is
shown in Figure 11. Wideband amplitude noise is summed with
the input data signal as shown in Figure 4. Performance is
shown for input data levels of 5 mV and 10 mV.
BINARY
OUTPUT
EPITAXX ERM504
SCOPE
PROBE AD807 QUANTIZER
VCM
VCM
2mVp-p
a. Single-Ended Input Application
BINARY
OUTPUT
AD8015
DIFFERENTIAL
OUTPUT TIA
SCOPE
PROBE AD807 QUANTIZER
VCM
VCM
1mVp-p
+OUT
–OUT
b. Differential Input Application
Figure 3. (a–b) Single-Ended and Differential Input
Applications
DIFFERENTIAL
SIGNAL
SOURCE
POWER
SPLITTER
NOISE
SOURCE
FILTER
100MHz
D.U.T.
AD807
POWER COMBINER
POWER
COMBINER
50
0.47µF
75
100
1.0µF
GND
+5V
PIN
NIN
+
+
+
50
0.47µF
Figure 4. Bit Error Rate vs. Signal-to-Noise Ratio
Test: Block Diagram
400
400
AVCC2
DIFFERENTIAL
INPUT
AVEE
CURRENT SOURCES
HEADROOM
≥ 0.7V
VBE
0.8V
0.5mA
1mA
0.5mA
a. Quantizer Differential Input Stage
5.9k
THRADJ
AVEE
94.6k
1.2V +VBE
b. Threshold Adjust
150
VCC1
SDOUT
VEE
IOL
IOH
150
c. Signal Detect Output (SDOUT)
450
450
VCC2
DIFFERENTIAL
OUTPUT
VEE
2.5mA
d. PLL Differential Output Stage—DATAOUT(N),
CLKOUT(N)
Figure 5. (a–d) Simplified Schematics


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