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MC81F4204M Datasheet(PDF) 93 Page - Finechips |
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MC81F4204M Datasheet(HTML) 93 Page - Finechips |
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93 / 150 page  MC81F4204 October 19, 2009 Ver.1.35 93 T0SCR TIMER 0 STATUS AND CONROL REGISTER 00B0H To enable the timer 0 match interrupt, you must set “1” to T0MIE(IENH.7). When the timer 0 match interrupt sub-routine is serviced, the timer 0 match interrupt request flag bit, T0MIR(IRQH.7), is automatically cleared. To enable the timer 0 overflow interrupt, you must set “1” to T0OVIE(IENH.6). When the timer 0 overflow interrupt sub-routine is serviced, the timer 0 overflow interrupt request flag bit, T0OVIF(IRQH.6), is automatically cleared. 7 6 5 4 3 2 1 0 T0SCR T0MOD T0MS T0CC T0CS Reset value: 00H R/W R/W R/W R/W R/W R/W R/W R/W - - Not used for MC81F4204 T0MS Timer 0 Mode Selection Bit 00: Interval mode (T0O) 01: PWM mode (OVF and match interrupt can occur) 1X: Capture mode (OVF can occur) T0CC Timer 0 Counter Clear Bit 0: No effect 1: Clear the Timer 0 counter (When write, automatically cleared “0” after being cleared counter) T0CS Timer 0 Clock Selection Bits 0000: Counter stop 0001: Not available 0010: Not available 0011: Not available 0100: Not available 0101: External clock (EC0) rising edge 0110: External clock (EC0) falling edge 0111: Not available 1000: fxx/2 1001: fxx/4 1010: fxx/8 1011: fxx/16 1100: fxx/32 1101: fxx/128 1110: fxx/512 1111: fxx/2048 Note : You must set the T0CC(T0SCR.4) bit after set T0DR register. The timer 0 counter value is compared with timer 0 buffer register instead of T0DR. And T0DR value is copied to timer 0 buffer register when 1)T0CC is set 2)T0OVIR is set 3) T0MIR is set. |
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