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MC81F4104S Datasheet(PDF) 85 Page - Finechips

Part No. MC81F4104S
Description  ABOV SEMICONDUCTOR
Download  118 Pages
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Manufacturer  FINECHIPS [Finechips]
Direct Link  http://www.finechips.com
Logo FINECHIPS - Finechips

MC81F4104S Datasheet(HTML) 85 Page - Finechips

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MC81F4104
October 19, 2009 Ver.1.35
85
19.2 Procedure
To do the A/D converting, follow these basic steps:
1.
Set the ADC pins as the alternative mode.
2.
Set the ADMR register for
- setting ADC channel
- setting Clock
- clearing the
„End of Conversion‟ bit
- starting ADC
3.
Wait until ADC is finished ( check the
„End of Conversion‟ bit )
When ADC is finished, EOC bit is set and SSBIT is cleared automatically.
4.
Read the ADCRH and ADCRL register
To initiate an analog-to-digital conversion procedure, at first you must set ADC pins to alternative
function (ADC analog input) mode. And you write the channel selection data in the A/D mode register
(ADMR) to select one of analog input channels and set the conversion start/stop bit, SSBIT. The pins
not used for ADC can be used for normal I/O.
To start the A/D conversion, you should set the start/stop bit, SSBIT. When a conversion is
completed, the end-of-conversion bit, EOC is automatically set to 1 and the result is dumped into the
ADDRH/ADDRL register. Then the A/D converter enters an idle state. The EOC bit is cleared when
SSBIT is set.
Note that, ADC interrupt is not provided.
Note :
Because the A/D converter has no sample-and-hold circuitry, it is very important that
fluctuation of the analog level at the AD0-AD2,AD4-AD7 input pins during a conversion
procedure be kept to an absolute minimum. Any change in the input level, perhaps due to
noise, will invalidate the result.
If the chip enters to STOP or IDLE mode in conversion process, there will be a leakage
current path in A/D block. You must use STOP or IDLE mode after ADC operation is
finished.
19.3 Conversion Timing
The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-
up A/D conversion. Therefore, total of 66 clocks are required to complete a 12-bit conversion: When
fxx/8 is selected for conversion clock with a 12 MHz fxx clock frequency, one clock cycle is 0.66
s.
Each bit conversion requires 4 clocks, the conversion rate is calculated as follows:
4 clocks/bit
 14 bits + set-up time = 66 clocks, 66 clock  0.66 s = 44.0 s at 1.5 MHz (12 MHz/8)
Note : The A/D converter needs at least 25
s for conversion time. So you must set the
conversion time slower than 25
s.


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