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MC81F4104 Datasheet(PDF) 89 Page - Finechips |
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MC81F4104 Datasheet(HTML) 89 Page - Finechips |
89 / 118 page ![]() MC81F4104 October 19, 2009 Ver.1.35 89 20.5 Power On Reset There is a internal power on reset circuit internally. We simply call it POR. POR occurs the reset event when VDD is rising over the POR level. Note that, POR can be enabled and disabled by the PORC register. And default setting is „POR enable ‟. So at the first time power is supplied, POR is working always even external reset is enabled. PORC POWER ON RESET CONTROL REGISTER (00F3H) 7 6 5 4 3 2 1 0 PORC One byte register Reset value:00H POR Enable/Disable 01011010: POR disable Others: POR enable Note : It is recommended to disable the POR. When POR is enabled, current consumption is increased and, the LVR(Low Voltage Reset) is ignored even the LVR is enabled by the „ROM OPTION ‟. 20.6 Low Voltage Reset The low voltage reset occurs the reset event when current VDD is going down under the LVR level. It is configurable by the rom-option. ( See „8. ROM OPTION‟ on page 33) If you want to know more detail timing information, see „7.8 LVR (Low Voltage Reset) Electrical Characteristics ‟ on page 24. Figure 20-4 LVR Timing Diagram at 4MHz system clock |
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