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MC81F4104 Datasheet(PDF) 70 Page - Finechips |
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MC81F4104 Datasheet(HTML) 70 Page - Finechips |
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70 / 118 page  MC81F4104 70 October 19, 2009 Ver.1.35 15. WATCH DOG TIMER M U X fxx/1024 fxx/512 fxx/256 fxx/128 fxx/64 fxx/32 fxx/16 fxx/8 fxx Start the CPU 8-Bit Up Counter BITR BTCL clear BTIR BTIE BTINT BCK[2:0] Watchdog Counter (7-bit) 7-bit Comparator 7-bit Compare data WDTR WDTCL clear clear WTIR WDTIE WDTINT overflow WDTSR To RESET CPU WDTON overflow Basic interval timer INT request Basic interval timer INT enable Watchdog timer INT request Watchdog timer INT enable The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset CPU or a interrupt request. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. The watchdog timer uses the Basic Interval Timer as a clock source. The watchdog timer consists of 7-bit binary counter and the watchdog timer data register. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as Watchdog timer interrupt or reset the CPU in accordance with the bit WDTON. Watchdog reset feature is disabled when the watchdog timer status register(WDTSR) value is „0A5h‟. Note that, WDTSR ‟s reset value is „00h‟. And reset value of WDTON is „1‟. So watchdog timer reset is enabled at reset time. Figure 15-1 Block diagram of Basic Interval Timer/Watchdog Timer |
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