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MC81F4104 Datasheet(PDF) 57 Page - Finechips

Part No. MC81F4104
Description  ABOV SEMICONDUCTOR
Download  118 Pages
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Manufacturer  FINECHIPS [Finechips]
Direct Link  http://www.finechips.com
Logo FINECHIPS - Finechips

MC81F4104 Datasheet(HTML) 57 Page - Finechips

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MC81F4104
October 19, 2009 Ver.1.35
57
11. INTERRUTP CONTROLLER
Watchdog Timer Interrupt
External Interrupt 1
External Interrupt 0
EXT0IR
EXT1IR
External Interrupt 2
EXT2IR
EXT0IE
Interrupt
Request
Interrupt
Enable
EXT1IE
EXT2IE
Timer2 matchInterrupt
T2MIR
T2OVIR
T2OVIE
T2MIE
Timer2 overflow Interrupt
Timer3 matchInterrupt
T3MIR
T3OVIR
T3OVIE
T3MIE
Timer3 overflow Interrupt
WDTIR
WDTIE
Release STOP/SLEEP
I-flag
Interrupt
Master
Enable
Flag
To CPU
Interrupt
Vector
Address
Generator
Basic Timer Interrupt
BTIR
BTIE
The MC81F4104 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request
flags of IRQH, IRQL, Priority circuit, and Master enable flag
(“I” flag of PSW). And 9 interrupt sources
are provided.
The interrupt vector addresses are shown in
„11.5 Interrupt Vector & Priority Table‟ on page 63.
Interrupt enable registers are shown in next paragraph. These registers are composed of interrupt
enable flags of each interrupt source and these flags determine whether an interrupt will be accepted
or not. When the
enable flag is “0”, a corresponding interrupt source is disabled.
Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once.
Figure 11-1 Block Diagram of Interrupt


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