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AD7890SQ-10 Datasheet(PDF) 10 Page - Analog Devices |
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AD7890SQ-10 Datasheet(HTML) 10 Page - Analog Devices |
10 / 20 page AD7890 –10– REV. A If the application requires a reference with a tighter tolerance or the AD7890 needs to be used with a system reference, then the user has the option of connecting an external reference to this REF OUT/REF IN pin. The external reference will effectively overdrive the internal reference and thus provide the reference source for the ADC. The reference input is buffered but has a nominal 2 k Ω resistor connected to the AD7890’s internal refer- ence. Suitable reference sources for the AD7890 include the AD680, AD780 and REF-43 precision +2.5 V references. Timing and Control Section The AD7890 is capable of two interface modes, selected by the SMODE input. The first of these is a self-clocking mode where the part provides the frame sync, serial clock and serial data at the end of conversion. In this mode the serial clock rate is determined by the master clock rate of the part (at CLK IN input). The second mode is an external clocking mode where the user provides the frame sync and serial clock signals to obtain the serial data from the part. In this second mode, the user has control of the serial clock rate up to a maximum of 10 MHz. The two modes are discussed in more detail in the Serial Interface section. The part also provides hardware and software conversion start features. The former provides a well-defined sampling instant with the track/hold going into hold on the rising edge of the CONVST signal. For the software conversion start, a write to the CONV bit to the Control Register initiates the conversion sequence. However, for the software conversion start an internal pulse has to time out before the input signal is sampled. This pulse, plus the difficult in maintaining exactly equal delays between each software conversion start command, means that the dynamic performance of the AD7890 may have difficulty meeting spec when used in software conversion start mode. The AD7890 provides separate channel select and conversion start control. This allows the user to optimize the throughput rate of the system. Once the track/hold has gone into hold mode, the input channel can be updated and the input voltage can settle to the new value while the present conversion is in progress. Assuming the internal pulse has timed out before the CONVST pulse is exercised, the conversion will consist of 14.5 master clock cycles. In the self-clocking mode, the conversion time is defined as the time from the rising edge of CONVST to the fall- ing edge of RFS (i.e., when the device starts to transmit its con- version result). This time includes the 14.5 master clock cycles plus the updating of the output register and delay time in out- putting the RFS signal, resulting in a total conversion time of 5.9 µs maximum. Figure 4 shows the conversion timing for the AD890 when used in the Self-Clocking (Master) Mode with hardware CONVST. The timing diagram assumes that the internal pulse is not active when the CONVST signal goes high. To ensure this, the channel address to be converted should be selected by writing to the Control Register prior to the CONVST pulse. Sufficient setup time should be allowed between the Control Register write and the CONVST to ensure that the internal pulse has timed out. The duration of the inter- nal pulse (and hence the duration of setup time) depends on the value of CEXT. Track/Hold Section The SHA IN input on the AD7890 connects directly to the input stage of the track/hold amplifier. This is a high impedance input with input leakage currents of less than 50 nA. Connect- ing the MUX OUT pin directly to the SHA IN pin connects the multiplexer output directly to the track/hold amplifier. The input voltage range for this input is 0 V to +2.5 V. If external circuitry is connected between MUX OUT and SHA IN, then the user must ensure that the input voltage range to the SHA IN input is 0 V to +2.5 V to ensure that the full dynamic range of the converter is utilized. The track/hold amplifier on the AD7890 allows the ADC to accurately convert an input sine wave of full-scale amplitude to 12-bit accuracy. The input bandwidth of the track/hold is greater than the Nyquist rate of the ADC even when the ADC is operated at its maximum throughput rate of 117 kHz (i.e., the track/hold can handle input frequencies in excess of 58 kHz). The track/hold amplifier acquires an input signal to 12-bit accu- racy in less than 2 µs. The operation of the track/hold is essen- tially transparent to the user. The track/hold amplifier goes from its tracking mode to its hold mode at the start of conversion. The start of conversion is the rising edge of CONVST (assum- ing the internal pulse has timed out) for hardware conversion starts and for software conversion starts is the point where the internal pulse is timed out. The aperture time for the track/hold (i.e., the delay time between the external CONVST signal and the track/hold actually going into hold) is typically 15 ns. For software conversion starts, the time depends on the internal pulse widths. Therefore, for software conversion starts, the sam- pling instant is not very well defined. For sampling systems which require well defined, equidistant sampling, it may not be possible to achieve optimum performance from the part using the software conversion start. At the end of conversion, the part returns to its tracking mode. The acquisition time of the track/ hold amplifier begins at this point. Reference Section The AD7890 contains a single reference pin, labelled REF OUT/REF IN, which either provides access to the part’s own +2.5 V reference or to which an external +2.5 V reference can be connected to provide the reference source for the part. The part is specified with a +2.5 V reference voltage. Errors in the reference source will result in gain errors in the AD7890’s transfer function and will add to the specified full-scale errors on the part. On the AD7893-10, it will also result in an offset error injected in the attenuator stage. The AD7890 contains an on-chip +2.5 V reference. To use this reference as the reference source for the AD7890, simply con- nect a 0.1 µF disc ceramic capacitor from the REF OUT/ REF IN pin to AGND. The voltage which appears at this pin is inter- nally buffered before being applied to the ADC. If this reference is required for use external to the AD7890, it should be buffered as the source impedance of this output is 2 k Ω nominal. The tolerance on the internal reference is ±10 mV at 25°C with a typical temperature coefficient of 25 ppm/ °C and a maximum error over temperature of ±25 mV. |
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