REV. B

AD7887

–4–

(A, B Versions)

Parameter

+4.75 V to +5.25 V

+2.7 V to +3.6 V

Units

Description

2

2

2

MHz max

10

10

ns min

CS to SCLK Setup Time

3

30

60

ns max

Delay from CS Until DOUT Three-State Disabled

3

75

100

ns max

Data Access Time after SCLK Falling Edge

20

20

ns min

Data Setup Time Prior to SCLK Rising Edge

20

20

ns min

Data Valid to SCLK Hold Time

ns min

SCLK High Pulsewidth

ns min

SCLK Low Pulsewidth

4

80

80

ns max

CS Rising Edge to DOUT High Impedance

55

µs typ

Power-Up Time from Shutdown

NOTES

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

the part and is independent of the bus loading.

Specifications subject to change without notice.

+1.6V

200 A

200 A

TO

OUTPUT

PIN

50pF

Figure 1. Load Circuit for Digital Output Timing Specifications