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AD7827BR Datasheet(PDF) 10 Page - Analog Devices |
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AD7827BR Datasheet(HTML) 10 Page - Analog Devices |
10 / 12 page AD7827 –10– REV. 0 AD7827 SERIAL INTERFACE In order to achieve a high throughput rate, the serial port of the AD7827 has been optimized for high speed serial protocols. Many high speed serial protocols use a continuous serial clock to transfer data, e.g., the serial ports of many popular DSPs like the TMS320C5x, ADSP-21xx and DSP560xx. The serial inter- face of the AD7827 is optimized for communication with such devices. The serial interface of the AD7827 uses a three-wire interface to communicate with a Master. The serial clock pin (SCLK) is a logic input and determines the bit transfer rate. The Receive Frame Synchronization pin (RFS) is a logic output and used to synchronize the data with a continuous serial clock. The data output pin (DOUT) is a logic output and serial data is shifted out onto this pin on the rising edge of the serial clock. The first rising edge of the serial clock after the end of a conversion causes the RFS pin to go logic low. (See Figure 15 below.) The DOUT pin leaves its high impedance state and the first MSB is shifted out on the first SCLK rising edge after the end of conversion. The remaining seven data bits are shifted out on subsequent SCLK rising edges. The DOUT pin enters its high impedance state again on the falling edge of the eighth SCLK after RFS goes low. The RFS output goes high again on the rising edge of the ninth SCLK. If the AD7827 does not receive a ninth SCLK, the RFS will be reset logic high by the next falling edge of CONVST. DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RFS SCLK DOUT CONVST t1 t2 t3 t7 t8 t4 t10 1 2345 6 7 8 t9 t5 t11 t6 Figure 15. Serial Timing |
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