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AD7810YRM Datasheet(PDF) 9 Page - Analog Devices |
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AD7810YRM Datasheet(HTML) 9 Page - Analog Devices |
9 / 11 page AD7810 –9– REV. A tPOWER-UP 1 s A B DOUT SCLK t1 CONVST CURRENT CONVERSION RESULT Figure 15. Mode 2 Operation Timing Mode 2 Operation (Automatic Power-Down) When used in this mode of operation, the part automatically powers down at the end of a conversion. This is achieved by leaving the CONVST signal low until the end of the conversion. Because it takes approximately 1 µs for the part to power up after it has been powered down, this mode of operation is in- tended to be used in applications where slower throughput rates are required, i.e., in the order of 100 kSPS. The timing diagram in Figure 15 shows how to operate the part in this mode. If the AD7810 is powered down, the rising edge of the CONVST pulse causes the part to power up. When the part has powered up ( ≈ 1 µs after the rising edge of CONVST), the CONVST signal is brought low, and a conversion is initiated on this falling edge of the CONVST signal. The conversion takes 2 µs and after this time, the conversion result is latched into the serial shift register and the part powers down. Therefore, when the part is operated in Mode 2, the effective conversion time is equal to the power-up time (1 µs) and the SAR conversion time (2 µs). NOTE: Although the AD7810 takes 1 µs to power up after the rising edge of CONVST, it is not necessary to leave CONVST high for 1 µs after the rising edge before bringing it low to ini- tiate a conversion. If the CONVST signal goes low before 1 µs in time has elapsed, then the power-up time is timed out internally and a conversion is then initiated. Hence the AD7810 is guaran- teed to have always powered up before a conversion is initiated— even if the CONVST pulse width is < 1 µs. If the CONVST width is > 1 µs, then a conversion is initiated on the falling edge. As in the case of Mode 1 operation, the rising edge of the CONVST pulse enables the serial port of the AD7810 (see Serial Interface section). If a serial read is initiated soon after this rising edge (Point “A”), i.e., before the end of the conver- sion, the result of the previous conversion is shifted out on pin DOUT. In order to read the result of the current conversion, the user must wait at least 2 µs after the falling edge of CONVST before initiating a serial read. The serial port of the AD7810 is still functional even though the AD7810 has been powered down. NOTE: Serial read should not cross the next rising edge of CONVST. Because it is possible to do a serial read from the part while it is powered down, the AD7810 is powered up only to do the conversion and is immediately powered down at the end of a conversion. This significantly improves the power consumption of the part at slower throughput rates—see Power vs. Through- put Rate section. SERIAL INTERFACE The serial interface of the AD7810 consists of three wires, a serial clock input SCLK, serial port enable CONVST and a serial data output DOUT (see Figure 16). The serial interface is designed to allow easy interfacing to most microcontrollers, e.g., PIC16C, PIC17C, QSPI and SPI, without the need for any gluing logic. When interfacing to the 8051, the SCLK must be inverted. The Microprocessor Interface section explains how to interface to some popular microcontrollers. Figure 16 shows the timing diagram for a serial read from the AD7810. The serial interface works with both a continuous and a noncontinuous serial clock. The rising edge of the CONVST signal resets a counter, which counts the number of serial clocks to ensure the correct number of bits are shifted out of the serial shift registers. The SCLK is ignored once the correct number of bits have been shifted out. In order for another serial transfer to take place, the counter must be reset by the falling edge of the 10th SCLK. Data is clocked out from the DOUT line on the first rising SCLK edge after the rising edge of the CONVST signal and on subsequent SCLK rising edges. DOUT enters its high impedance state again on the falling edge of the 10th SCLK. In multipackage applications, the CONVST signal can be used as a chip select signal. The serial interface will not shift data out until it receives a rising edge on the CONVST pin. CONVST DOUT SCLK t8 12 3 4 5 6 7 8 9 10 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB9 DB8 t3 t4 t7 t6 t5 Figure 16. AD7810 Serial Interface Timing |
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