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DTP4N60 Datasheet(PDF) 6 Page - DinTek Semiconductor Co,.Ltd |
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DTP4N60 Datasheet(HTML) 6 Page - DinTek Semiconductor Co,.Ltd |
6 / 8 page 6 Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms Fig. 12c - Maximum Avalanche Energy vs. Drain Current Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit R g IAS 0.01 Ω tp D.U.T. L V DS + - V DD 10 V Vary tp to obtain required IAS IAS VDS VDD VDS tp 1200 0 200 400 600 800 1000 25 150 125 100 75 50 Starting TJ, Junction Temperature (°C) Bottom Top I D 1.8 A 2.9 A 4 A V DD = 50 V 91114_12c Q GS Q GD Q G VG Charge 10 V D.U.T. 3 mA V GS V DS I G I D 0.3 µF 0.2 µF 50 k Ω 12 V Current regulator Current sampling resistors Same type as D.U.T. + - D www. daysemi.jp |
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