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CYRF89435 Datasheet(PDF) 4 Page - Cypress Semiconductor |
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CYRF89435 Datasheet(HTML) 4 Page - Cypress Semiconductor |
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4 / 40 page  CYRF89435 Document Number: 001-76581 Rev. *D Page 4 of 40 PSoC® Functional Overview The PSoC family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (MCU)-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The architecture for this device family, as shown in the Logical Block Diagram on page 2, consists of three main areas: ■ The Core ■ CapSense Analog System ■ WirelessUSB NL System ■ System Resources. A common, versatile bus allows connection between I/O and the analog system. Each CYRF89435 device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. The 13 GPIOs provide access to the MCU and analog mux. PSoC Core The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO and ILO. The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvard-architecture microprocessor. CapSense System The analog system contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. The analog system is composed of the CapSense PSoC block and an internal 1 V or 1.2 V analog reference, which together support capacitive sensing of up to 13 inputs. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins are completed quickly and easily across multiple ports. SmartSense SmartSense is an innovative solution from Cypress that removes manual tuning of CapSense applications. This solution is easy to use and provides a robust noise immunity. It is the only auto-tuning solution that establishes, monitors, and maintains all required tuning parameters. SmartSense allows engineers to go from prototyping to mass production without re-tuning for manufacturing variations in PCB and/or overlay material properties. SmartSense_EMC In addition to the SmartSense auto-tuning algorithm to remove manual tuning of CapSense applications, SmartSense_EMC user module incorporates a unique algorithm to improve robustness of capacitive sensing algorithm/circuit against high frequency conducted and radiated noise. Every electronic device must comply with specific limits for radiated and conducted external noise and these limits are specified by regulatory bodies (for example, FCC, CE, U/L and so on). A very good PCB layout design, power supply design and system design is a mandatory for a product to pass the conducted and radiated noise tests. An ideal PCB layout, power supply design or system design is not often possible because of cost and form factor limitations of the product. SmartSense_EMC with superior noise immunity is well suited and handy for such applications to pass radiated and conducted noise test. Figure 1. CapSense System Block Diagram IDAC Reference Buffer Vr Cinternal Cap Sense Counters Comparator Mux Mux Refs CapSense Clock Select Oscillator CSCLK IMO CS1 CS2 CSN Cexternal (P0[1] or P0[3]) |
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