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AD7677 Datasheet(PDF) 4 Page - Analog Devices

Part No. AD7677
Description  16-Bit, 1 LSB INL, 1 MSPS Differential ADC
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7677 Datasheet(HTML) 4 Page - Analog Devices

 
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REV. 0
AD7677
–4–
TIMING SPECIFICATIONS
Symbol
Min
Typ
Max
Unit
Refer to Figures 11 and 12
Convert Pulsewidth
t1
5ns
Time Between Conversions
t2
1/1.25/1.5
Note 1
µs
(Warp Mode/Normal Mode/Impulse Mode)
CNVST LOW to BUSY HIGH Delay
t3
30
ns
BUSY HIGH All Modes Except in
t4
0.75/1/1.25
µs
Master Serial Read after Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
t5
2ns
End of Conversion to BUSY LOW Delay
t6
10
ns
Conversion Time
t7
0.75/1/1.25
µs
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
t8
250
ns
RESET Pulsewidth
t9
10
ns
Refer to Figures 13, 14, and 15 (Parallel Interface Modes)
CNVST LOW to DATA Valid Delay
t10
0.75/1/1.25
µs
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
t11
45
ns
Bus Access Request to DATA Valid
t12
40
ns
Bus Relinquish Time
t13
515
ns
Refer to Figures 17 and 18 (Master Serial Interface Modes)
2
CS LOW to SYNC Valid Delay
t14
10
ns
CS LOW to Internal SCLK Valid Delay
t15
10
ns
CS LOW to SDOUT Delay
t16
10
ns
CNVST LOW to SYNC Delay (Read During Convert)
t17
25/275/525
ns
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay3
t18
3ns
Internal SCLK Period
3
t19
25
40
ns
Internal SCLK HIGH
3
t20
12
ns
Internal SCLK LOW3
t21
7ns
SDOUT Valid Setup Time
3
t22
4ns
SDOUT Valid Hold Time
3
t23
2ns
SCLK Last Edge to SYNC Delay3
t24
3
CS HIGH to SYNC HI-Z
t25
10
ns
CS HIGH to Internal SCLK HI-Z
t26
10
ns
CS HIGH to SDOUT HI-Z
t27
10
ns
BUSY HIGH in Master Serial Read After Convert
3
t28
See Table I
CNVST LOW to SYNC Asserted Delay
t29
0.75/1/1.25
µs
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
t30
25
ns
Refer to Figures 19 and 20 (Slave Serial Interface Modes)
External SCLK Setup Time
t31
5ns
External SCLK Active Edge to SDOUT Delay
t32
318
ns
SDIN Setup Time
t33
5ns
SDIN Hold Time
t34
5ns
External SCLK Period
t35
25
ns
External SCLK HIGH
t36
10
ns
External SCLK LOW
t37
10
ns
NOTES
1In warp mode only, the maximum time between conversions is 1 ms, otherwise, there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L of 10 pF; otherwise, the load is 60 pF maximum.
3In serial master read during convert mode. See Table I for serial master read after convert mode.
Specifications subject to change without notice.
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise stated.)


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