PCAL9555APW datasheet(10/46 Pages) NXP

Part #	PCAL9555APW

Description	Low-voltage 16-bit I2C-bus GPIO with Agile I/O, interrupt and weak pull-up

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Manufacturer	NXP [NXP Semiconductors]

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PCAL9555A

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Product data sheet

Rev. 1 — 3 October 2012

10 of 46

NXP Semiconductors

PCAL9555A

Low-voltage 16-bit GPIO with Agile I/O, interrupt and weak pull-up

cleared, assuming there were no additional input(s) that have changed, and bit 4 of the

input port 0 register will read ‘1’. The next read of the input port 0 register bit 4 register

should now read ‘0’.

An interrupt remains active when a non-latched input simultaneously switches state with a

latched input and then returns to its original state. A read of the input register reflects only

the change of state of the latched input and also clears the interrupt. The interrupt is not

cleared if the input latch register changes from latched to non-latched configuration. If the

input pin is changed from latched to non-latched input, a read from the input port register

reflects the current port logic level. If the input pin is changed from non-latched to latched

input, the read from the input register reflects the latched logic level. A register pair write is

described in Section 7.1 and a register pair read is described in Section 7.2.

6.2.8 Pull-up/pull-down enable register pair (46h, 47h)

These registers allow the user to enable or disable pull-up/pull-down resistors on the I/O

pins. Setting the bit to logic 1 enables the selection of pull-up/pull-down resistors. Setting

the bit to logic 0 disconnects the pull-up/pull-down resistors from the I/O pins. Also, the

resistors will be disconnected when the outputs are configured as open-drain outputs (see

Section 6.2.12). Use the pull-up/pull-down registers to select either a pull-up or pull-down

resistor. A register pair write is described in Section 7.1 and a register pair read is

described in Section 7.2.

Table 17.

Input latch port 0 register (address 44h)

Bit

7

6

5

4

3

2

1

0

Symbol

L0.7

L0.6

L0.5

L0.4

L0.3

L0.2

L0.1

L0.0

Default

00

Table 18.

Input latch port 1 register (address 45h)

Bit

7

6

5

4

3

2

1

0

Symbol

L1.7

L1.6

L1.5

L1.4

L1.3

L1.2

L1.1

L1.0

Default

00

Table 19.

Pull-up/pull-down enable port 0 register (address 46h)

Bit

7

6

5

4

3

2

1

0

Symbol

PE0.7

PE0.6

PE0.5

PE0.4

PE0.3

PE0.2

PE0.1

PE0.0

Default

11

Table 20.

Pull-up/pull-down enable port 1 register (address 47h)

Bit

7

6

5

4

3

2

1

0

Symbol

PE1.7

PE1.6

PE1.5

PE1.4

PE1.3

PE1.2

PE1.1

PE1.0

Default

11

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