PCAL9555A datasheet(9/46 Pages) NXP

Part #	PCAL9555A

Description	Low-voltage 16-bit I2C-bus GPIO with Agile I/O, interrupt and weak pull-up

Download	46 Pages

Scroll/Zoom	100%

Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

Logo

9 / 46 page

PCAL9555A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1 — 3 October 2012

9 of 46

NXP Semiconductors

PCAL9555A

Low-voltage 16-bit GPIO with Agile I/O, interrupt and weak pull-up

6.2.6 Output drive strength register pairs (40h, 41h, 42h, 43h)

The Output drive strength registers control the output drive level of the GPIO. Each GPIO

can be configured independently to a certain output current level by two register control

bits. For example, Port 0.7 is controlled by register 41 bits CC0.7 (bits [7:6]), Port 0.6 is

controlled by register 41 CC0.6(bits [5:4]). The output drive level of the GPIO is

programmed 00b = 0.25

, 01b = 0.50, 10b = 0.75, or 11b = 1 of the maximum drive

capability of the I/O. See Section 8.2 “Output drive strength control”. A register pair write is

described in Section 7.1 and a register pair read is described in Section 7.2.

6.2.7 Input latch register pair (44h, 45h)

The input latch registers (registers 44 and 45) enable and disable the input latch of the I/O

pins. These registers are effective only when the pin is configured as an input port. When

an input latch register bit is 0, the corresponding input pin state is not latched. A state

change of the corresponding input pin generates an interrupt. A read of the input register

clears the interrupt. If the input goes back to its initial logic state before the input port

register is read, then the interrupt is cleared.

When an input latch register bit is 1, the corresponding input pin state is latched. A change

of state in the input generates an interrupt and the input logic value is loaded into the

corresponding bit of the input port register (registers 0 and 1). A read of the input port

register clears the interrupt. If the input pin returns to its initial logic state before the input

port register is read, then the interrupt is not cleared and the corresponding bit of the input

port register keeps the logic value that initiated the interrupt. See Figure 12 “Read input

port register (latch enabled), scenario 3”.

For example, if the P0_4 input was as logic 0 and the input goes to logic 1 then back to

logic 0, the input port 0 register will capture this change and an interrupt is generated (if

unmasked). When the read is performed on the input port 0 register, the interrupt is

Table 13.

Current control port 0 register (address 40h)

Bit

7

6

5

4

3

2

1

0

Symbol

CC0.3

CC0.2

CC0.1

CC0.0

Default

11

Table 14.

Current control port 0 register (address 41h)

Bit

7

6

5

4

3

2

1

0

Symbol

CC0.7

CC0.6

CC0.5

CC0.4

Default

11

Table 15.

Current control port 1 register (address 42h)

Bit

7

6

5

4

3

2

1

0

Symbol

CC1.3

CC1.2

CC1.1

CC1.0

Default

11

Table 16.

Current control port 1 register (address 43h)

Bit

7

6

5

4

3

2

1

0

Symbol

CC1.7

CC1.6

CC1.5

CC1.4

Default

11

Similar Part No. - PCAL9555A

Manufacturer	Part #	Datasheet	Description
NXP Semiconductors	PCAL9555A	727Kb / 8P	Smart, simple solutions for the 12 most common design concerns August 2011

More results

Similar Description - PCAL9555A

Manufacturer	Part #	Datasheet	Description
NXP Semiconductors	PCA9555A	2Mb / 39P	Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up Rev. 1-11 September 2012
	PCAL9554B	2Mb / 42P	Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up and Agile I/O Rev. 2-10 December 2012
	PCAL9535A	2Mb / 46P	Low-voltage 16-bit I2C-bus I/O port with interrupt and Agile I/O Rev. 1-28 September 2012
	PCA9554B	2Mb / 36P	Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, weak pull-up Rev. 1-19 September 2012
	PCAL9538A	2Mb / 43P	Low-voltage 8-bit I2C-bus and SMBus low power I/O port with interrupt, reset and Agile I/O Rev. 2-10 December 2012
	PCA9535A	2Mb / 38P	Low-voltage 16-bit I2C-bus I/O port with interrupt Rev. 1-11 September 2012
	PCA9539A	2Mb / 39P	Low-voltage 16-bit I2C-bus I/O port with interrupt and reset Rev. 1-26 September 2012
Texas Instruments	TCAL6416	1Mb / 42P	[Old version datasheet] TCAL6416 Low-Voltage Translating, 16-Bit I2C-Bus/SMBus I/O Expander with Interrupt Output, Reset, and Agile I/O Configuration Registers JUNE 2022
Nuvoton Technology Corp...	NCT5655Y	836Kb / 26P	16-bit I2C-bus and SMBus GPIO controller with interrupt
Texas Instruments	TCAL6416	1Mb / 43P	[Old version datasheet] TCAL6416 Low-Voltage Translating, 16-Bit I2C-Bus/SMBus I/O Expander with Interrupt Output, Reset, and Agile I/O Configuration Registers JUNE 2022

More results

PCAL9555A Datasheet(PDF) 9 Page - NXP Semiconductors

PCAL9555A Datasheet(HTML) 9 Page - NXP Semiconductors

Similar Part No. - PCAL9555A

Similar Description - PCAL9555A

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL